SHA2 256bit fully pipelined 320 layer architecture

simulatable and synthesizable portable VHDL code
pipeline elements are separately optimized and contain 5 level pipeline each
the full pipeline consists of 64 pipeline elements
calculates 320 separate input stream's hashes parallelly
compression pipeline input can be initialized with arbitrary intermediate hash state

Applied optimizations

only 2 input adders are used in the entire design, to enable high speed FPGA implementation
most of the shift registers have been replaced with distributed RAMs based circular buffers to decrease unnecessary bit flipping and with that power consumption

pipeline length to be a parameterizable multiple of 5
optional swicthing between shift registers and circular buffer to better match with FPGA resources (some LUTs can only be applied as shift registers)

This is code is meant to be a know-how sample and is not to be used in its current form for free.

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
LUT5x32w2out.vhd		LUT5x32w2out.vhd
README.md		README.md
comp_pipe_element.png		comp_pipe_element.png
distRAM4x32w2cnt.vhd		distRAM4x32w2cnt.vhd
distRAM5x32w2cnt.vhd		distRAM5x32w2cnt.vhd
sha256_comp_pipe.vhd		sha256_comp_pipe.vhd
sha256_comp_pipe_element.vhd		sha256_comp_pipe_element.vhd
sha256_full_sim_test.vhd		sha256_full_sim_test.vhd
sha256_full_top.vhd		sha256_full_top.vhd
sha256_hw_test.vhd		sha256_hw_test.vhd
sha256_nlfsr_pipe.vhd		sha256_nlfsr_pipe.vhd
sha256_nlfsr_pipe_element.vhd		sha256_nlfsr_pipe_element.vhd
simulation_results.PNG		simulation_results.PNG
synthesis_on_Artix-200.PNG		synthesis_on_Artix-200.PNG
w_pipe_0.png		w_pipe_0.png
w_pipe_1.png		w_pipe_1.png
w_pipe_2.png		w_pipe_2.png
w_pipe_3.png		w_pipe_3.png
w_pipe_4.png		w_pipe_4.png