update the FireSim docs to account for the removal of FireBoom DUT

firesim · Oct 9, 2019 · 7666669 · davidbiancolin · Oct 9, 2019 · 7666669
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diff --git a/docs/Advanced-Usage/Debugging/DESSERT.rst b/docs/Advanced-Usage/Debugging/DESSERT.rst
@@ -31,7 +31,7 @@ below:
 
 ::
 
-    id: 1190, module: IssueSlot_4, path: FireBoomNoNIC.tile_1.core.issue_units_0.slots_3]
+    id: 1190, module: IssueSlot_4, path: FireSimNoNIC.tile_1.core.issue_units_0.slots_3]
     Assertion failed
         at issue_slot.scala:214 assert (!slot_p1_poisoned)
         at cycle: 2142042185

diff --git a/docs/Advanced-Usage/Debugging/RTL-Simulation.rst b/docs/Advanced-Usage/Debugging/RTL-Simulation.rst
@@ -221,7 +221,7 @@ Scala Tests
 
 To make it easier to do RTL-simulation-based regression testing, the scala
 tests wrap calls to Makefiles, and run a limited set of tests on a set of selected
-designs, including all of the MIDAS examples, FireSimNoNIC and FireBoomNoNIC.
+designs, including all of the MIDAS examples and FireSimNoNIC.
 
 The selected tests, target configurations, as well as the type of RTL simulator
 to compile can be modified by changing the scala tests that reside at

diff --git a/docs/Advanced-Usage/Generating-Different-Targets.rst b/docs/Advanced-Usage/Generating-Different-Targets.rst
@@ -147,19 +147,19 @@ Quad-core, Rocket pipeline
 BOOM-based SoCs
 ---------------
 
-Two design classes use BOOM (`Berkeley Out-of-Order Machine <https://github.com/ucb-bar/riscv-boom>`_) superscalar out-of-order pipelines.
+The BOOM (`Berkeley Out-of-Order Machine <https://github.com/ucb-bar/riscv-boom>`_) superscalar out-of-order pipelines can also be used with the same design classes that the Rocket pipelines use.
 
 Single-core BOOM
 
 ::
 
-    make DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig
+    make DESIGN=FireSim TARGET_CONFIG=FireSimBoomConfig
 
 Single-core BOOM, no network interface
 
 ::
 
-    make DESIGN=FireBoomNoNIC TARGET_CONFIG=FireSimBoomConfig
+    make DESIGN=FireSimNoNIC TARGET_CONFIG=FireSimBoomConfig
 
 
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