Fixed invalid memory access of MMIO port addresses

[nandor]

UART no longer keeps a reference. Fixed the typo causing the invalid access.

Related PRs / Issues

UI / API Impact

Verilog / AGFI Compatibility

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[davidbiancolin]

@abejgonzalez This need ci:fpga-deploy

[davidbiancolin]

@nandor, thanks. Could you add a bounds check in simif somewhere? That could help catch future problems in lieu of better testing.

[nandor]

I've created #1318 to follow up on this.