VCS and Verilator DPI switchover

sim/midas/src/main/cc/Makefile

@@ -54,24 +54,24 @@ override CXXFLAGS += -std=c++17 -include $(design_h)
 # Models of FPGA primitives that are used in host-level sim, but not in FPGATop
 sim_fpga_resource_models := $(v_dir)/BUFGCE.v
 
-emul_files := simif simif_emul emul/mmio emul/mm emul/context
+emul_files := simif simif_emul emul/mmio emul/mm
 emul_h     := $(driver_h) $(bridge_h) $(addprefix $(midas_dir)/, $(addsuffix .h, $(emul_files)))
 # This includes c sources and static libraries
 emul_cc    := $(DRIVER) $(bridge_cc) $(addprefix $(midas_dir)/, $(addsuffix .cc, $(emul_files)))
 emul_v     := $(design_vh) $(design_v) $(sim_fpga_resource_models)
 
 verilator_conf := rtlsim/ml-verilator-conf.vlt
-verilator_wrapper_v := $(v_dir)/verilator_top.sv
-verilator_harness := simif_emul_verilator.cc
-top_module := verilator_top
+verilator_wrapper_v := $(v_dir)/top.sv
+verilator_harness := emul/dpi.cc simif_emul_verilator.cc
+top_module := emul
 include rtlsim/Makefrag-verilator
 
 verilator: $(OUT_DIR)/V$(DRIVER_NAME)
 verilator-debug: $(OUT_DIR)/V$(DRIVER_NAME)-debug
 
 # Add an extra wrapper source for VCS simulators
-vcs_wrapper_v := $(v_dir)/vcs_top.sv
-vcs_harness := emul/vcs-harness.cc simif_emul_vcs.cc
+vcs_wrapper_v := $(v_dir)/top.sv
+vcs_harness := emul/dpi.cc simif_emul_vcs.cc
 TB := emul
 VCS_FLAGS := -e vcs_main
 include rtlsim/Makefrag-vcs