Fixes needed to support Scala 2.13

sim/midas/src/main/scala/junctions/addrmap.scala

@@ -97,7 +97,7 @@ class AddrMap(
       prot |= r.attr.prot
       cacheable &&= r.attr.cacheable
     }
-    (base - start, rebasedEntries, MemAttr(prot, cacheable))
+    (base - start, rebasedEntries.toSeq, MemAttr(prot, cacheable))
   }
 
   val flatten: Seq[AddrMapEntry] = {

sim/midas/src/main/scala/midas/passes/AnnotationWiringTransform.scala

@@ -86,7 +86,7 @@ class AnnotationParameterizedWiringTransform[
     }
 
     doWiring() match {
-      case Success(state) => state.copy(annotations = cleanedAnnotations)
+      case Success(state) => state.copy(annotations = cleanedAnnotations.toSeq)
       case Failure(why) =>
         throw new RuntimeException(s"Could not perform wiring for annotation: ${wiringKey}. Exception follows.\n $why")
     }

sim/midas/src/main/scala/midas/passes/AssertionSynthesis.scala

@@ -13,7 +13,7 @@ import firrtl.Utils.{zero, to_flip, BoolType}
 
 import freechips.rocketchip.config.{Parameters, Field}
 
-import Utils._
+import midas.passes.Utils.cat
 import midas.widgets.{BridgeIOAnnotation, AssertBridgeRecord, AssertBridgeModule, AssertBridgeParameters}
 import midas.passes.fame.{FAMEChannelConnectionAnnotation, WireChannel}
 import midas.stage.phases.ConfigParametersAnnotation

sim/midas/src/main/scala/midas/passes/AutoCounterTransform.scala

@@ -124,7 +124,7 @@ class AutoCounterTransform extends Transform with AutoCounterConsts {
           def printEnable = Neq(WRef(target.ref), WRef(reg))
           generatePrintf(label, clock, WRef(target.ref), printEnable, target.ref + "_identity_print")
       }
-      m.copy(body = Block(m.body, addedStmts:_*))
+      m.copy(body = Block(m.body, addedStmts.toSeq:_*))
     case o => o
   }
 
@@ -226,7 +226,7 @@ class AutoCounterTransform extends Transform with AutoCounterConsts {
     }
 
     val updatedCircuit = c.copy(modules = c.modules.map({
-      case m: Module if m.name == c.main => m.copy(ports = m.ports ++ addedPorts, body = Block(m.body, addedStmts:_*))
+      case m: Module if m.name == c.main => m.copy(ports = m.ports ++ addedPorts, body = Block(m.body, addedStmts.toSeq:_*))
       case o => o
     }))
 
@@ -267,12 +267,12 @@ class AutoCounterTransform extends Transform with AutoCounterConsts {
     covermodulesnames.foreach({ i => println(s"  ${i}") })
 
     //collect annotations for manually annotated AutoCounter perf counters
-    val filteredCounterAnnos =  counterAnnos.filter(_.shouldBeIncluded(covermodulesnames))
+    val filteredCounterAnnos =  counterAnnos.filter(_.shouldBeIncluded(covermodulesnames.toSeq))
     println(s"[AutoCounter] selected ${filteredCounterAnnos.length} signals for instrumentation")
     filteredCounterAnnos.foreach({ i => println(s"  ${i}") })
 
     // group the selected signal by modules, and attach label from the cover point to each signal
-    val selectedsignals = filteredCounterAnnos.groupBy(_.enclosingModule())
+    val selectedsignals = filteredCounterAnnos.groupBy(_.enclosingModule()).map { case (k, v) => k -> v.toSeq }
 
     if (!selectedsignals.isEmpty) {
       println(s"[AutoCounter] signals are:")
@@ -284,8 +284,8 @@ class AutoCounterTransform extends Transform with AutoCounterConsts {
       // Common preprocessing: gate all annotated events with their associated reset
       val updatedAnnos = new mutable.ArrayBuffer[AutoCounterFirrtlAnnotation]()
       val updatedModules = state.circuit.modules.map((gateEventsWithReset(selectedsignals, updatedAnnos)))
-      val eventModuleMap = updatedAnnos.groupBy(_.enclosingModule())
-      val gatedState = state.copy(circuit = state.circuit.copy(modules = updatedModules), annotations = remainingAnnos)
+      val eventModuleMap = updatedAnnos.groupBy(_.enclosingModule()).map { case (k, v) => k -> v.toSeq}
+      val gatedState = state.copy(circuit = state.circuit.copy(modules = updatedModules), annotations = remainingAnnos.toSeq)
 
       val preppedState = (new ResolveAndCheck).runTransform(gatedState)
 

sim/midas/src/main/scala/midas/passes/BridgeTopWiring.scala

@@ -190,7 +190,7 @@ class BridgeTopWiring(val prefix: String) extends firrtl.Transform {
 
     val updatedCircuit = c.copy(modules = c.modules.map({
       case m: Module if m.name == c.main => m.copy(ports = m.ports ++ addedPorts,
-                                                   body  = Block(m.body, addedConnects:_*))
+                                                   body  = Block(m.body, addedConnects.toSeq:_*))
       case o => o
     }))
 

sim/midas/src/main/scala/midas/passes/SimulationMapping.scala

@@ -17,7 +17,7 @@ import firrtl.Mappers._
 import firrtl.passes.LowerTypes.loweredName
 import firrtl.Utils.{BoolType, splitRef, mergeRef, create_exps, flow, module_type}
 import firrtl.passes.wiring._
-import Utils._
+import midas.passes.Utils._
 import chisel3.stage.{ChiselGeneratorAnnotation, NoRunFirrtlCompilerAnnotation}
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.LazyModule

sim/midas/src/main/scala/midas/passes/TriggerWiring.scala

@@ -120,7 +120,7 @@ private[passes] object TriggerWiring extends firrtl.Transform {
     } else {
       // Step 1) Gate credits and debits with their associated reset, if provided
       val updatedAnnos = new mutable.ArrayBuffer[TriggerSourceAnnotation]()
-      val srcAnnoMap = (srcCreditAnnos ++ srcDebitAnnos).groupBy(_.enclosingModule())
+      val srcAnnoMap = (srcCreditAnnos ++ srcDebitAnnos).groupBy(_.enclosingModule()).map { case (k, v) => k -> v.toSeq }
       val gatedCircuit = state.circuit.map(gateEventsWithReset(srcAnnoMap, updatedAnnos))
       val (gatedCredits, gatedDebits) = updatedAnnos.partition(_.sourceType)
 
@@ -226,11 +226,11 @@ private[passes] object TriggerWiring extends firrtl.Transform {
       val triggerSource = DefNode(NoInfo, triggerName, Neq(totalCredit, totalDebit))
       val triggerSourceRT = ModuleTarget(topModName, topModName).ref(triggerName)
       addedStmts += triggerSource
-      val topModWithTrigger = wiredTopModule.copy(ports = prexistingPorts, body = Block(portRemovedBody,  addedStmts:_*))
+      val topModWithTrigger = wiredTopModule.copy(ports = prexistingPorts, body = Block(portRemovedBody,  addedStmts.toSeq:_*))
       val updatedCircuit = wiredState.circuit.copy(modules = topModWithTrigger +: otherModules)
 
       // Step 8) Wire the generated trigger to all sinks using the WiringTranform
-      val sinkModuleMap = sinkAnnos.groupBy(_.target.module)
+      val sinkModuleMap = sinkAnnos.groupBy(_.target.module).map { case (k, v) => k -> v.toSeq }
       val wiringAnnos = new mutable.ArrayBuffer[Annotation]
       wiringAnnos += SourceAnnotation(triggerSourceRT.toNamed, sinkWiringKey)
       val preSinkWiringCircuit = updatedCircuit.map(onModuleSink(sinkModuleMap, wiringAnnos))

sim/midas/src/main/scala/midas/passes/fame/LabelSRAMModels.scala

@@ -62,7 +62,7 @@ class LabelSRAMModels extends Transform {
         m.copy(body = m.body.map(onStmt))
       case m => m
     })
-    val transformedCircuit = circ.copy(modules = memModules ++ transformedModules)
+    val transformedCircuit = circ.copy(modules = (memModules ++ transformedModules).toSeq)
     // At this point, the FIRRTLMemModelAnnotations are no longer used, so remove them for cleanup.
     val filteredAnnos = state.annotations.filterNot(_.isInstanceOf[FirrtlMemModelAnnotation])
     state.copy(circuit = transformedCircuit, annotations = filteredAnnos ++ memModelAnnotations)

sim/midas/src/main/scala/midas/widgets/ChannelizedHostPort.scala

@@ -48,7 +48,7 @@ trait ChannelizedHostPortIO extends HasChannels { this: Record =>
   private val channels = mutable.ArrayBuffer[(Data, ChannelType[_ <: Data], PipeChannelMetadata)]()
 
   // These will only be called after the record has been finalized.
-  lazy private val fieldToChannelMap = Map((channels.map(t => t._1 -> t._2)):_*)
+  lazy private val fieldToChannelMap = Map((channels.map(t => t._1 -> t._2)).toSeq:_*)
   private def reverseElementMap = elements.map({ case (chName, chField) => chField -> chName  }).toMap
 
   private def getLeafDirs(token: Data): Seq[Direction] = token match {

sim/midas/src/main/scala/midas/widgets/HostPort.scala

@@ -109,11 +109,11 @@ class HostPortIO[+T <: Data](private val targetPortProto: T) extends Record with
 
     // Dequeue from toHost channels only if all toHost tokens are available,
     // and the bridge consumes it
-    val toHostHelper   = DecoupledHelper((toHost.hReady +: toHostChannels.map(_.valid)):_*)
+    val toHostHelper   = DecoupledHelper((toHost.hReady +: toHostChannels.map(_.valid)).toSeq:_*)
     toHostChannels.foreach(ch => ch.ready := toHostHelper.fire(ch.valid))
 
     // Enqueue into the toHost channels only once all toHost channels can accept the token
-    val fromHostHelper = DecoupledHelper((fromHost.hValid +: fromHostChannels.map(_.ready)):_*)
+    val fromHostHelper = DecoupledHelper((fromHost.hValid +: fromHostChannels.map(_.ready)).toSeq:_*)
     fromHostChannels.foreach(ch => ch.valid := fromHostHelper.fire(ch.ready))
 
     // Tie off the target clock; these should be unused in the BridgeModule

sim/midas/src/main/scala/midas/widgets/Lib.scala

@@ -280,8 +280,8 @@ class MCRFileMap(bytesPerAddress: Int) {
     val regAddrs = regList map (reg => reg -> (base + lookupAddress(reg.name).get))
     val readRegs = regAddrs filter (_._1.permissions.readable)
     val writeRegs = regAddrs filter (_._1.permissions.writeable)
-    emitArrays(readRegs, prefix + "_R")
-    emitArrays(writeRegs, prefix + "_W")
+    emitArrays(readRegs.toSeq, prefix + "_R")
+    emitArrays(writeRegs.toSeq, prefix + "_W")
   }
 
   // Returns a copy of the current register map