stage_ID.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2018/03/08 17:54:41
// Design Name:
// Module Name: stage_ID
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


//inst_op
`define OP_ANDR		   6'h00 // レジスタ同士の論理??�??�?
`define OP_ANDI		   6'h01 // レジスタと定数の論理??�??�?
`define OP_ORR		   6'h02 // レジスタ同士の論理??�??�?
`define OP_ORI		   6'h03 // レジスタと定数の論理??�??�?
`define OP_XORR		   6'h04 // レジスタ同士の排他的論理??�??�?
`define OP_XORI		   6'h05 // レジスタと定数の排他的論理??�??�?
`define OP_ADDSR	   6'h06 // レジスタ同士の符号付き??�??�???�?
`define OP_ADDSI	   6'h07 // レジスタと定数の符号付き??�??�???�?
`define OP_ADDUR	   6'h08 // レジスタ同士の符号なし加??�??�?
`define OP_ADDUI	   6'h09 // レジスタと定数の符号なし加??�??�?
`define OP_SUBSR	   6'h0a // レジスタ同士の符号付き減�??�?
`define OP_SUBUR	   6'h0b // レジスタ同士の符号なし減�??�?
`define OP_SHRLR	   6'h0c // レジスタ同士の論理右シフト
`define OP_SHRLI	   6'h0d // レジスタと定数の論理右シフト
`define OP_SHLLR	   6'h0e // レジスタ同士の論理左シフト
`define OP_SHLLI	   6'h0f // レジスタと定数の論理左シフト
`define OP_BE		     6'h10 // レジスタ同士の符号付き比�??�?==)
`define OP_BNE		   6'h11 // レジスタ同士の符号付き比�??�?!=)
`define OP_BSGT		   6'h12 // レジスタ同士の符号付き比�??�?<)
`define OP_BUGT		   6'h13 // レジスタ同士の符号なし比�??�?<)
`define OP_JMP		   6'h14 // レジスタ??�??�???�??�??�?絶対??�??�???�?
`define OP_CALL		   6'h15 // レジスタ??�??�???�??�??�?サブルーチンコール
`define OP_LDW		   6'h16 // ワード読み出??�??�?
`define OP_STW		   6'h17 // ワード書き込み
`define OP_TRAP		   6'h18 // トラ??�??�??
`define OP_RDCR		   6'h19 // 制御レジスタの読み出??�??�?
`define OP_WRCR		   6'h1a // 制御レジスタへの書き込み
`define OP_EXRT		   6'h1b // 例外から�?復帰


//ALU Operation
`define ALU_OP_NOP			 4'h0 // No Operation
`define ALU_OP_AND			 4'h1 // AND
`define ALU_OP_OR			 4'h2 // OR
`define ALU_OP_XOR			 4'h3 // XOR
`define ALU_OP_ADDS			 4'h4 // 符号付き??�??�???�?
`define ALU_OP_ADDU			 4'h5 // 符号なし加??�??�?
`define ALU_OP_SUBS			 4'h6 // 符号付き減�??�?
`define ALU_OP_SUBU			 4'h7 // 符号なし減�??�?
`define ALU_OP_SHRL			 4'h8 // 論理右シフト
`define ALU_OP_SHLL			 4'h9 // 論理左シフト

//exec mode
`define CPU_KERNEL_MODE 0

`define EXP_NO_EXP	   3'h0	 // 例外な??�??�?
`define EXP_EXT_INT	   3'h1	 // 外部割り込み
`define EXP_UNDEF_INSN 3'h2	 // 未定義命令
`define EXP_OVERFLOW   3'h3	 // 算術オーバフロー
`define EXP_MISS_ALIGN 3'h4	 // アドレスミスアライン
`define EXP_TRAP	   3'h5	 // トラ??�??�??
`define EXP_PRV_VIO	   3'h6	 // 特権違反

/*
mem_op
0:NOP
1:LDW
2:STW
*/

`define WORD 32  // 1word
`define WORD_ADDR_W 30  // address width 1word

`define GPR_ADDR_MSB 5-1

`define WORD_MSB `WORD-1
`define WORD_ADDR_MSB `WORD_ADDR_W-1
`define RegAddrBus `GPR_ADDR_MSB:0

module decoder_ID (
	input [`WORD_ADDR_MSB:0]if_pc,
	input [`WORD_MSB:0]if_inst,
	input if_en,

	input[`WORD_MSB:0] gpr_rd_data_0,
	input[`WORD_MSB:0] gpr_rd_data_1,
	output [`GPR_ADDR_MSB:0] gpr_addr_0,
	output [`GPR_ADDR_MSB:0] gpr_addr_1,

	input id_en,
	input [`GPR_ADDR_MSB:0]id_dst_addr,
	input id_gpr_we,
	input [1:0]id_mem_op,

    input ex_en,
    input [`GPR_ADDR_MSB:0]ex_dst_addr,
    input ex_gpr_we,
    input [`WORD_MSB:0]ex_fwd_data,

    input [`WORD_MSB:0]mem_fwd_data,

    input exe_mode,
	input [`WORD_MSB:0]creg_rd_data,
	output reg[`GPR_ADDR_MSB:0] creg_rd_addr,

	output reg[3:0] alu_op,
	output reg[`WORD_MSB:0] alu_in_0,
	output reg[`WORD_MSB:0] alu_in_1,
	output reg[`WORD_ADDR_MSB:0] br_addr,
	output reg br_taken,
	output reg br_flag,
	output reg[1:0] mem_op,
	output reg[`WORD_MSB:0] mem_wr_data,
	output reg [1:0]ctrl_op,
	output reg [`GPR_ADDR_MSB:0]dst_addr,
	output reg gpr_we,
  output reg[2:0] exp_code,
  output reg ld_hazard
    );

    wire[5:0] op=if_inst[31:26];
    wire[4:0] ra_addr=if_inst[25:21],rb_addr=if_inst[20:16],rc_addr=if_inst[15:11];
    wire[15:0]imm=if_inst[15:0];

    wire[`WORD_MSB:0]imm_s={{16{imm[15]}},imm};//signed
    wire[`WORD_MSB:0]imm_u={16'b0,imm};//unsigned

     reg[`WORD_MSB:0]ra;
     wire signed[`WORD_MSB:0]s_ra=$signed(ra);
     reg[`WORD_MSB:0]rb;
     wire signed[`WORD_ADDR_MSB:0]s_rb=$signed(rb);//signed

     wire[`WORD_ADDR_MSB:0]ret_addr=if_pc+1;
     wire[`WORD_ADDR_MSB:0]br_target=if_pc+imm_s[`WORD_ADDR_MSB:0];
     wire[`WORD_ADDR_MSB:0]jmp_target=ra[`WORD_ADDR_MSB:0];

		 //fowording
		 always @ ( * ) begin
		 //ra regster
		 	if(id_en &&id_gpr_we && id_dst_addr==ra_addr) ra=ex_fwd_data;
			else if(ex_en &&ex_gpr_we && ex_dst_addr==ra_addr) ra=mem_fwd_data;
			else ra=gpr_rd_data_0;

			//rb regster
 		 	if(id_en &&id_gpr_we && id_dst_addr==rb_addr) rb=ex_fwd_data;
 			else if(ex_en &&ex_gpr_we && ex_dst_addr==rb_addr) rb=mem_fwd_data;
 			else rb=gpr_rd_data_1;
		 end

		 //detect load ld_hazard
		 always @ ( * ) begin
		 	if(id_en && id_mem_op ==1&& (id_dst_addr==ra_addr||id_dst_addr==rb_addr))ld_hazard=1;
			else ld_hazard=0;
		 end

		 //instraction decoder
		 always @ ( * ) begin
		 	alu_op=0;
			alu_in_0=ra;
			alu_in_1=rb;
			br_taken=0;
			br_flag=0;
			mem_op=0;
			ctrl_op=0;
			dst_addr=rb_addr;//R2
			gpr_we=0;
			exp_code=0;

			if (if_en == 1) begin
				case (op)
					/* ???�_???�???�???�???�???�Z???�???�???�???� */
					`OP_ANDR  : begin // ???�???�???�W???�X???�^???�???�???�m???�̘_???�???�???�???�
						alu_op	 = `ALU_OP_AND;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_ANDI  : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̘_???�???�???�???�
						alu_op	 = `ALU_OP_AND;
						alu_in_1 = imm_u;
						gpr_we	 = 1;
					end
					`OP_ORR	  : begin // ???�???�???�W???�X???�^???�???�???�m???�̘_???�???�???�a
						alu_op	 = `ALU_OP_OR;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_ORI	  : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̘_???�???�???�a
						alu_op	 = `ALU_OP_OR;
						alu_in_1 = imm_u;
						gpr_we	 = 1;
					end
					`OP_XORR  : begin // ???�???�???�W???�X???�^???�???�???�m???�̔r???�???�???�I???�_???�???�???�a
						alu_op	 = `ALU_OP_XOR;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_XORI  : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̔r???�???�???�I???�_???�???�???�a
						alu_op	 = `ALU_OP_XOR;
						alu_in_1 = imm_u;
						gpr_we	 = 1;
					end
					/* ???�Z???�p???�???�???�Z???�???�???�???� */
					`OP_ADDSR : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�t???�???�???�???�???�Z
						alu_op	 = `ALU_OP_ADDS;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_ADDSI : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̕�???�???�???�t???�???�???�???�???�Z
						alu_op	 = `ALU_OP_ADDS;
						alu_in_1 = imm_s;
						gpr_we	 = 1;
					end
					`OP_ADDUR : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�Ȃ�???�???�???�Z
						alu_op	 = `ALU_OP_ADDU;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_ADDUI : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̕�???�???�???�Ȃ�???�???�???�Z
						alu_op	 = `ALU_OP_ADDU;
						alu_in_1 = imm_s;
						gpr_we	 = 1;
					end
					`OP_SUBSR : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�t???�???�???�???�???�Z
						alu_op	 = `ALU_OP_SUBS;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_SUBUR : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�Ȃ�???�???�???�Z
						alu_op	 = `ALU_OP_SUBU;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					/* ???�V???�t???�g???�???�???�???� */
					`OP_SHRLR : begin // ???�???�???�W???�X???�^???�???�???�m???�̘_???�???�???�E???�V???�t???�g
						alu_op	 = `ALU_OP_SHRL;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_SHRLI : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̘_???�???�???�E???�V???�t???�g
						alu_op	 = `ALU_OP_SHRL;
						alu_in_1 = imm_u;
						gpr_we	 = 1;
					end
					`OP_SHLLR : begin // ???�???�???�W???�X???�^???�???�???�m???�̘_???�???�???�???�???�V???�t???�g
						alu_op	 = `ALU_OP_SHLL;
						dst_addr = rc_addr;
						gpr_we	 = 1;
					end
					`OP_SHLLI : begin // ???�???�???�W???�X???�^???�Ƒ�???�l???�̘_???�???�???�???�???�V???�t???�g
						alu_op	 = `ALU_OP_SHLL;
						alu_in_1 = imm_u;
						gpr_we	 = 1;
					end
					/* ???�???�???�򖽗� */
					`OP_BE	  : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�t???�???�???�???�???�r???�iRa == Rb???�j
						br_addr	 = br_target;
						br_taken = (ra == rb) ? 1 : 0;
						br_flag	 = 1;
					end
					`OP_BNE	  : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�t???�???�???�???�???�r???�iRa != Rb???�j
						br_addr	 = br_target;
						br_taken = (ra != rb) ? 1 : 0;
						br_flag	 = 1;
					end
					`OP_BSGT  : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�t???�???�???�???�???�r???�iRa < Rb???�j
						br_addr	 = br_target;
						br_taken = (s_ra < s_rb) ? 1 : 0;
						br_flag	 = 1;
					end
					`OP_BUGT  : begin // ???�???�???�W???�X???�^???�???�???�m???�̕�???�???�???�Ȃ�???�???�???�r???�iRa < Rb???�j
						br_addr	 = br_target;
						br_taken = (ra < rb) ? 1 : 0;
						br_flag	 = 1;
					end
					`OP_JMP	  : begin // ???�???�???�???�???�???�???�???�???�???�
						br_addr	 = jmp_target;
						br_taken = 1;
						br_flag	 = 1;
					end
					`OP_CALL  : begin // ???�R???�[???�???�
						alu_in_0 = {ret_addr, {2{1'b0}}};
						br_addr	 = jmp_target;
						br_taken = 1;
						br_flag	 = 1;
						dst_addr = 5'd31;
						gpr_we	 = 1;
					end
					/* ???�???�???�???�???�???�???�A???�N???�Z???�X???�???�???�???� */
					`OP_LDW	  : begin // ???�???�???�[???�h???�ǂݏo???�???�
						alu_op	 = `ALU_OP_ADDU;
						alu_in_1 = imm_s;
						mem_op	 = 1;
						gpr_we	 = 1;
					end
					`OP_STW	  : begin // ???�???�???�[???�h???�???�???�???�???�???�???�???�
						alu_op	 = `ALU_OP_ADDU;
						alu_in_1 = imm_s;
						mem_op	 = 2;
					end
					/* ???�V???�X???�e???�???�???�R???�[???�???�???�???�???�???� */
					`OP_TRAP  : begin // ???�g???�???�???�b???�v
						exp_code = `EXP_TRAP;
					end
					/* ???�???�???�???�???�???�???�???� */
					`OP_RDCR  : begin // ???�???�???�䃌�W???�X???�^???�̓ǂݏo???�???�
						if (exe_mode == `CPU_KERNEL_MODE) begin
							alu_in_0 = creg_rd_data;
							gpr_we	 = 1;
						end else begin
							exp_code = `EXP_PRV_VIO;
						end
					end
					`OP_WRCR  : begin // ???�???�???�䃌�W???�X???�^???�ւ̏�???�???�???�???�???�???�
						if (exe_mode == `CPU_KERNEL_MODE) begin
							ctrl_op	 = 1; //write ctrl reg
						end else begin
							exp_code = `EXP_PRV_VIO;
						end
					end
					`OP_EXRT  : begin // ???�???�???�O???�???�???�???�???�̕�???�A
						if (exe_mode == `CPU_KERNEL_MODE) begin
							ctrl_op	 = 2;//return from exception
						end else begin
							exp_code = `EXP_PRV_VIO;
						end
					end
					/* ???�???�???�̑�???�̖�???�???� */
					default		  : begin // ???�???�???�???�???�`???�???�???�???�
						exp_code = `EXP_UNDEF_INSN;
					end
				endcase
			end
		 end

endmodule //decoder_ID


module reg_ID (
	input clk,
	input rst,

	output reg[3:0] alu_op,
	output reg[`WORD_MSB:0] alu_in_0,
	output reg[`WORD_MSB:0] alu_in_1,
	//output reg[`WORD_ADDR_MSB:0] br_addr,
	output reg br_flag,
	output reg[1:0] mem_op,
	output reg[`WORD_MSB:0] mem_wr_data,
	output reg [1:0]ctrl_op,
	output reg [`GPR_ADDR_MSB:0]dst_addr,
	output reg gpr_we,
	input[2:0] exp_code,

    input stall,
    input flush,

	input [`WORD_ADDR_MSB:0]if_pc,
	input if_en,

	output reg [`WORD_ADDR_MSB:0]id_pc,
	output reg id_en,

	output reg[3:0] id_alu_op,
	output reg[`WORD_MSB:0] id_alu_in_0,
	output reg[`WORD_MSB:0] id_alu_in_1,
	output reg id_br_flag,

	output reg [1:0]id_mem_op,
	output reg [`WORD_MSB:0]id_mem_wr_data,

	output reg [1:0] id_ctrl_op,
	output reg [`GPR_ADDR_MSB:0]id_dst_addr,

	output reg id_gpr_we,
  output reg [2:0]id_exp_code

    );


		  always@(posedge clk or negedge rst)begin//bus access control
		    if(~rst)begin
		      id_pc<=0;
		      id_en<=0;
					id_alu_op<=0;
					id_alu_in_0<=0;
					id_alu_in_1<=0;
					id_br_flag<=0;
					id_mem_op<=0;
					id_mem_wr_data<=0;
					id_ctrl_op<=0;
					id_dst_addr<=0;
					id_gpr_we<=0;
					id_exp_code<=0;
				end
		    else if(~stall)begin
					if(flush)begin
						id_pc<=0;
		      	id_en<=0;
						id_alu_op<=0;
						id_alu_in_0<=0;
						id_alu_in_1<=0;
						id_br_flag<=0;
						id_mem_op<=0;
						id_mem_wr_data<=0;
						id_ctrl_op<=0;
						id_dst_addr<=0;
						id_gpr_we<=0;
						id_exp_code<=0;
					end
					else begin
						id_pc<=if_pc;
						id_en<=if_en;
						id_alu_op<=alu_op;
						id_alu_in_0<=alu_in_0;
						id_alu_in_1<=alu_in_1;
						id_br_flag<=br_flag;
						id_mem_op<=mem_op;
						id_mem_wr_data<=mem_wr_data;
						id_ctrl_op<=ctrl_op;
						id_dst_addr<=dst_addr;
						id_gpr_we<=gpr_we;
						id_exp_code<=exp_code;
					end
				end
			end
endmodule
module stage_ID(
	input  wire					 clk,			 // ?N???b?N
	input  wire					 reset,			 // ??????Z?b?g
	/********** GPR?C???^?t?F?[?X **********/
	input  wire [`WORD_MSB:0]	 gpr_rd_data_0,	 // ???o???f?[?^ 0
	input  wire [`WORD_MSB:0]	 gpr_rd_data_1,	 // ???o???f?[?^ 1
	output wire [`GPR_ADDR_MSB:0]	 gpr_rd_addr_0,	 // ???o???A?h???X 0
	output wire [`GPR_ADDR_MSB:0]	 gpr_rd_addr_1,	 // ???o???A?h???X 1
	/********** ?t?H???[?f?B???O **********/
	// EX?X?e?[?W??????t?H???[?f?B???O
	input  wire					 ex_en,			// ?p?C?v???C???f?[?^??L??
	input  wire [`WORD_MSB:0]	 ex_fwd_data,	 // ?t?H???[?f?B???O?f?[?^
	input  wire [`GPR_ADDR_MSB:0]	 ex_dst_addr,	 // ????????A?h???X
	input  wire					 ex_gpr_we_,	 // ????????L??
	// MEM?X?e?[?W??????t?H???[?f?B???O
	input  wire [`WORD_MSB:0]	 mem_fwd_data,	 // ?t?H???[?f?B???O?f?[?^
	/********** ?????W?X?^?C???^?t?F?[?X **********/
	input  wire exe_mode,		 // ???s???[?h
	input  wire [`WORD_MSB:0]	 creg_rd_data,	 // ???o???f?[?^
	output wire [`GPR_ADDR_MSB:0]	 creg_rd_addr,	 // ???o???A?h???X
	/********** ?p?C?v???C???????M?? **********/
	input  wire					 stall,			 // ?X?g?[??
	input  wire					 flush,			 // ?t???b?V??
	output wire [`WORD_ADDR_MSB:0]	 br_addr,		 // ?????A?h???X
	output wire					 br_taken,		 // ?????????
	output wire					 ld_hazard,		 // ???[?h?n?U?[?h
	/********** IF/ID?p?C?v???C?????W?X?^ **********/
	input  wire [`WORD_ADDR_MSB:0]	 if_pc,			 // ?v???O?????J?E???^
	input  wire [`WORD_MSB:0]	 if_insn,		 // ????
	input  wire					 if_en,			 // ?p?C?v???C???f?[?^??L??
	/********** ID/EX?p?C?v???C?????W?X?^ **********/
	output wire [`WORD_ADDR_MSB:0]	 id_pc,			 // ?v???O?????J?E???^
	output wire					 id_en,			 // ?p?C?v???C???f?[?^??L??
	output wire [3:0]		 id_alu_op,		 // ALU?I?y???[?V????
	output wire [`WORD_MSB:0]	 id_alu_in_0,	 // ALU???? 0
	output wire [`WORD_MSB:0]	 id_alu_in_1,	 // ALU???? 1
	output wire					 id_br_flag,	 // ?????t???O
	output wire [1:0]		 id_mem_op,		 // ???????I?y???[?V????
	output wire [`WORD_MSB:0]	 id_mem_wr_data, // ??????????????f?[?^
	output wire [1:0]	 id_ctrl_op,	 // ?????I?y???[?V????
	output wire [`GPR_ADDR_MSB:0]	 id_dst_addr,	 // GPR????????A?h???X
	output wire					 id_gpr_we_,	 // GPR????????L??
	output wire [2:0]	 id_exp_code	 // ???O?R?[?h
);

	/********** ?f?R?[?h?M?? **********/
	wire  [3:0]			 alu_op;		 // ALU?I?y???[?V????
	wire  [`WORD_MSB:0]		 alu_in_0;		 // ALU???? 0
	wire  [`WORD_MSB:0]		 alu_in_1;		 // ALU???? 1
	wire						 br_flag;		 // ?????t???O
	wire  [1:0]			 mem_op;		 // ???????I?y???[?V????
	wire  [`WORD_MSB:0]		 mem_wr_data;	 // ??????????????f?[?^
	wire  [1:0]			 ctrl_op;		 // ?????I?y???[?V????
	wire  [`GPR_ADDR_MSB:0]			 dst_addr;		 // GPR????????A?h???X
	wire						 gpr_we_;		 // GPR????????L??
	wire  [2:0]			 exp_code;		 // ???O?R?[?h

	/********** ?f?R?[?_ **********/
	decoder_ID decoder (
		/********** IF/ID?p?C?v???C?????W?X?^ **********/
		.if_pc			(if_pc),		  // ?v???O?????J?E???^
		.if_inst		(if_insn),		  // ????
		.if_en			(if_en),		  // ?p?C?v???C???f?[?^??L??
		/********** GPR?C???^?t?F?[?X **********/
		.gpr_rd_data_0	(gpr_rd_data_0),  // ???o???f?[?^ 0
		.gpr_rd_data_1	(gpr_rd_data_1),  // ???o???f?[?^ 1
		.gpr_addr_0	(gpr_rd_addr_0),  // ???o???A?h???X 0
		.gpr_addr_1	(gpr_rd_addr_1),  // ???o???A?h???X 1
		/********** ?t?H???[?f?B???O **********/
		// ID?X?e?[?W??????t?H???[?f?B???O
		.id_en			(id_en),		  // ?p?C?v???C???f?[?^??L??
		.id_dst_addr	(id_dst_addr),	  // ????????A?h???X
		.id_gpr_we		(id_gpr_we_),	  // ????????L??
		.id_mem_op		(id_mem_op),	  // ???????I?y???[?V????
		// EX?X?e?[?W??????t?H???[?f?B???O
		.ex_en			(ex_en),		  // ?p?C?v???C???f?[?^??L??
		.ex_fwd_data	(ex_fwd_data),	  // ?t?H???[?f?B???O?f?[?^
		.ex_dst_addr	(ex_dst_addr),	  // ????????A?h???X
		.ex_gpr_we		(ex_gpr_we_),	  // ????????L??
		// MEM?X?e?[?W??????t?H???[?f?B???O
		.mem_fwd_data	(mem_fwd_data),	  // ?t?H???[?f?B???O?f?[?^
		/********** ?????W?X?^?C???^?t?F?[?X **********/
		.exe_mode		(exe_mode),		  // ???s???[?h
		.creg_rd_data	(creg_rd_data),	  // ???o???f?[?^
		.creg_rd_addr	(creg_rd_addr),	  // ???o???A?h???X
		/********** ?f?R?[?h?M?? **********/
		.alu_op			(alu_op),		  // ALU?I?y???[?V????
		.alu_in_0		(alu_in_0),		  // ALU???? 0
		.alu_in_1		(alu_in_1),		  // ALU???? 1
		.br_addr		(br_addr),		  // ?????A?h???X
		.br_taken		(br_taken),		  // ?????????
		.br_flag		(br_flag),		  // ?????t???O
		.mem_op			(mem_op),		  // ???????I?y???[?V????
		.mem_wr_data	(mem_wr_data),	  // ??????????????f?[?^
		.ctrl_op		(ctrl_op),		  // ?????I?y???[?V????
		.dst_addr		(dst_addr),		  // ??p???W?X?^????????A?h???X
		.gpr_we		(gpr_we_),		  // ??p???W?X?^????????L??
		.exp_code		(exp_code),		  // ???O?R?[?h
		.ld_hazard		(ld_hazard)		  // ???[?h?n?U?[?h
	);

	/********** ?p?C?v???C?????W?X?^ **********/
	reg_ID id_reg (
		/********** ?N???b?N & ???Z?b?g **********/
		.clk			(clk),			  // ?N???b?N
		.rst			(reset),		  // ??????Z?b?g
		/********** ?f?R?[?h???? **********/
		.alu_op			(alu_op),		  // ALU?I?y???[?V????
		.alu_in_0		(alu_in_0),		  // ALU???? 0
		.alu_in_1		(alu_in_1),		  // ALU???? 1
		.br_flag		(br_flag),		  // ?????t???O
		.mem_op			(mem_op),		  // ???????I?y???[?V????
		.mem_wr_data	(mem_wr_data),	  // ??????????????f?[?^
		.ctrl_op		(ctrl_op),		  // ?????I?y???[?V????
		.dst_addr		(dst_addr),		  // ??p???W?X?^????????A?h???X
		.gpr_we		(gpr_we_),		  // ??p???W?X?^????????L??
		.exp_code		(exp_code),		  // ???O?R?[?h
		/********** ?p?C?v???C???????M?? **********/
		.stall			(stall),		  // ?X?g?[??
		.flush			(flush),		  // ?t???b?V??
		/********** IF/ID?p?C?v???C?????W?X?^ **********/
		.if_pc			(if_pc),		  // ?v???O?????J?E???^
		.if_en			(if_en),		  // ?p?C?v???C???f?[?^??L??
		/********** ID/EX?p?C?v???C?????W?X?^ **********/
		.id_pc			(id_pc),		  // ?v???O?????J?E???^
		.id_en			(id_en),		  // ?p?C?v???C???f?[?^??L??
		.id_alu_op		(id_alu_op),	  // ALU?I?y???[?V????
		.id_alu_in_0	(id_alu_in_0),	  // ALU???? 0
		.id_alu_in_1	(id_alu_in_1),	  // ALU???? 1
		.id_br_flag		(id_br_flag),	  // ?????t???O
		.id_mem_op		(id_mem_op),	  // ???????I?y???[?V????
		.id_mem_wr_data (id_mem_wr_data), // ??????????????f?[?^
		.id_ctrl_op		(id_ctrl_op),	  // ?????I?y???[?V????
		.id_dst_addr	(id_dst_addr),	  // ??p???W?X?^????????A?h???X
		.id_gpr_we		(id_gpr_we_),	  // ??p???W?X?^????????L??
		.id_exp_code	(id_exp_code)	  // ???O?R?[?h
	);

endmodule