Merge branch 'dev-v2020.2'

fpgadeveloper · Jan 19, 2021 · 7827260 · 7827260
2 parents 0db23d0 + e6dc6b5
commit 7827260
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diff --git a/.gitignore b/.gitignore
@@ -0,0 +1,17 @@
+Vivado/.Xil/
+Vivado/*.log
+Vivado/*.jou
+Vivado/axi_eth_*/
+Vivado/ps_gem_*/
+PetaLinux/axi_eth_*/
+PetaLinux/ps_gem_*/
+Vitis/.*/
+Vitis/.*
+Vitis/embeddedsw/
+Vitis/boot/
+Vitis/axi_eth_*/
+Vitis/ps_gem_*/
+Vitis/RemoteSystemsTempFiles/
+Vitis/*.log
+Vitis/*.jou
+
diff --git a/EmbeddedSw/README.md b/EmbeddedSw/README.md
@@ -0,0 +1,21 @@
+Modified BSP files
+==================
+
+### lwIP modifications
+
+This project uses a modified version of the lwIP library. The modifications allow it to work for our MDIO
+bus architecture where a single master is connected to multiple slaves.
+
+### AXI Ethernet driver modifications
+
+The AXI Ethernet driver is also modified to allow support of the common master MDIO architecture. To do this
+we add an extra pointer to the XAxiEthernet struct (AXI Ethernet driver instance data) that points to the
+base address of the XAxiEthernet that is master of the MDIO bus. The MDIO read and write functions are changed to
+refer to this base address rather than the base address of the instance passed.
+
+### EMAC PS driver modifications
+
+The EMAC PS driver is also modified to allow support of the common master MDIO architecture. To do this
+we add an extra pointer to the XEmacPs struct (XEmacPs driver instance data) that points to the
+base address of the XEmacPs that is master of the MDIO bus. The MDIO read and write functions (XEmacPs_PhyRead,
+XEmacPs_PhyWrite) are changed to refer to this base address rather than the base address of the instance passed.
diff --git a/...w_services/lwip211_v1_19/data/lwip211.mld → ...w_services/lwip211_v1_39/data/lwip211.mld b/...w_services/lwip211_v1_19/data/lwip211.mld → ...w_services/lwip211_v1_39/data/lwip211.mld
@@ -1,27 +1,6 @@
 ###############################################################################
-#
-# Copyright (C) 2007 - 2019 Xilinx, Inc.  All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-# THE SOFTWARE.
-#
-#
-#
+# Copyright (c) 2007 - 2020 Xilinx, Inc.  All rights reserved.
+# SPDX-License-Identifier: MIT
 ###############################################################################
 
 OPTION psf_version = 2.1;
@@ -33,7 +12,7 @@ BEGIN LIBRARY lwip211
   OPTION desc = "lwip211 library: lwIP (light weight IP) is an open source TCP/IP stack configured for Xilinx hard and soft Ethernet MACs";
   OPTION app_linker_flags = "-Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group";
   OPTION requires_os = (standalone xilkernel freertos10_xilinx);
-  OPTION VERSION = 1.19;
+  OPTION VERSION = 1.39;
   OPTION NAME = lwip211;
 
   PARAM name = api_mode, desc = "Mode of operation for lwIP (RAW API/Sockets API)", type = enum, values = ("RAW API" = RAW_API, "SOCKET API" = SOCKET_API), default = RAW_API;

diff --git a/...b/ports/xilinx/include/netif/xaxiemacif.h → ...b/ports/xilinx/include/netif/xaxiemacif.h b/...b/ports/xilinx/include/netif/xaxiemacif.h → ...b/ports/xilinx/include/netif/xaxiemacif.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * Copyright (C) 2010 - 2020 Xilinx, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -71,6 +71,7 @@ err_t 	xaxiemacif_init(struct netif *netif);
 int 	xaxiemacif_input(struct netif *netif);
 
 unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp, u32 sgmii_phy_addr, u32 ext_phy_addr);
+void enable_sgmii_clock(XAxiEthernet *xaxiemacp);
 unsigned configure_IEEE_phy_speed(XAxiEthernet *xaxiemacp, u32 sgmii_phy_addr, u32 ext_phy_addr, unsigned speed);
 unsigned phy_setup_axiemac (XAxiEthernet *xaxiemacp);
 

diff --git a/...c/contrib/ports/xilinx/netif/xaxiemacif.c → ...c/contrib/ports/xilinx/netif/xaxiemacif.c b/...c/contrib/ports/xilinx/netif/xaxiemacif.c → ...c/contrib/ports/xilinx/netif/xaxiemacif.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * Copyright (C) 2010 - 2020 Xilinx, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -354,6 +354,10 @@ static err_t low_level_init(struct netif *netif)
 	XAxiEthernet_Initialize(&xaxiemacif->axi_ethernet, mac_config,
 				mac_config->BaseAddress);
 
+#ifdef XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT
+	//enable_sgmii_clock(&xaxiemacif->axi_ethernet);
+#endif
+
 	/* figure out if the system has DMA */
 	if (XAxiEthernet_IsDma(&xaxiemacif->axi_ethernet)) {
 #ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_DMA