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cad/py-cocotb: New port: Coroutine based cosimulation library for wri…
…ting VHDL and Verilog
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PORTNAME= cocotb | ||
DISTVERSIONPREFIX= v | ||
DISTVERSION= 1.7.2 | ||
CATEGORIES= cad python | ||
PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} | ||
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MAINTAINER= yuri@FreeBSD.org | ||
COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog | ||
WWW= https://www.cocotb.org/ | ||
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LICENSE= BSD3CLAUSE | ||
LICENSE_FILE= ${WRKSRC}/LICENSE | ||
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BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR} | ||
RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \ | ||
gtkwave:cad/gtkwave | ||
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USES= python:3.6+ | ||
USE_PYTHON= pep517 autoplist pytest # https://github.com/cocotb/cocotb/issues/3230 | ||
USE_GITHUB= yes | ||
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TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR} | ||
TEST_WRKSRC= ${WRKSRC}/tests | ||
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OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO | ||
OPTIONS_DEFAULT= IVERILOG VERILATOR | ||
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IVERILOG_DESC= Iverilog dependency | ||
IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog | ||
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VERILATOR_DESC= Verilator dependency | ||
VERILATOR_RUN_DEPENDS= verilator:cad/verilator | ||
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post-install: | ||
@${STRIP_CMD} \ | ||
${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \ | ||
${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \ | ||
${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl | ||
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.include <bsd.port.mk> |
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TIMESTAMP = 1675490974 | ||
SHA256 (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 2b72f25e91a8733abc9a49171adcf67d04670eb64bdc6be0d8ee653ac6b1d69f | ||
SIZE (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 641521 |
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cocotb is an open source coroutine-based cosimulation testbench environment | ||
for verifying VHDL and SystemVerilog RTL using Python. | ||
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cocotb lets you verify chips like software: productive, simulator-agnostic, | ||
in Python. |