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cad/py-cocotb: New port: Coroutine based cosimulation library for wri…
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…ting VHDL and Verilog
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yurivict committed Feb 4, 2023
1 parent 3604fc3 commit 0ad876d
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1 change: 1 addition & 0 deletions cad/Makefile
Expand Up @@ -102,6 +102,7 @@
SUBDIR += pcb-rnd
SUBDIR += pdnmesh
SUBDIR += py-cadquery
SUBDIR += py-cocotb
SUBDIR += py-cq-editor
SUBDIR += py-edalize
SUBDIR += py-ezdxf
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40 changes: 40 additions & 0 deletions cad/py-cocotb/Makefile
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PORTNAME= cocotb
DISTVERSIONPREFIX= v
DISTVERSION= 1.7.2
CATEGORIES= cad python
PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX}

MAINTAINER= yuri@FreeBSD.org
COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog
WWW= https://www.cocotb.org/

LICENSE= BSD3CLAUSE
LICENSE_FILE= ${WRKSRC}/LICENSE

BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR}
RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \
gtkwave:cad/gtkwave

USES= python:3.6+
USE_PYTHON= pep517 autoplist pytest # https://github.com/cocotb/cocotb/issues/3230
USE_GITHUB= yes

TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR}
TEST_WRKSRC= ${WRKSRC}/tests

OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO
OPTIONS_DEFAULT= IVERILOG VERILATOR

IVERILOG_DESC= Iverilog dependency
IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog

VERILATOR_DESC= Verilator dependency
VERILATOR_RUN_DEPENDS= verilator:cad/verilator

post-install:
@${STRIP_CMD} \
${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \
${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \
${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl

.include <bsd.port.mk>
3 changes: 3 additions & 0 deletions cad/py-cocotb/distinfo
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TIMESTAMP = 1675490974
SHA256 (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 2b72f25e91a8733abc9a49171adcf67d04670eb64bdc6be0d8ee653ac6b1d69f
SIZE (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 641521
5 changes: 5 additions & 0 deletions cad/py-cocotb/pkg-descr
@@ -0,0 +1,5 @@
cocotb is an open source coroutine-based cosimulation testbench environment
for verifying VHDL and SystemVerilog RTL using Python.

cocotb lets you verify chips like software: productive, simulator-agnostic,
in Python.

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