Chisel v6.5.0

Features

• Don't ... top of stack trace if it isn't actually trimmed (backport #4142) (by @mergify[bot] in #4143)
• PeekPokeAPI: include source location on failed expect() calls. (backport #4144) (by @mergify[bot] in #4149)
  SimulationData.expect calls now record source location and report it in the FailedExpectationException on failure.
• Preserve literals across .asUInt (backport #4148) (by @mergify[bot] in #4150)
  This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and .fir size.
• Preserve literal value across .asSInt and .zext (backport #4151) (by @mergify[bot] in #4152)
• Preserve UInt and SInt literals across .pad (backport #4156) (by @mergify[bot] in #4157)
• Add support for marking things as readOnly (backport #4190) (by @mergify[bot] in #4194)
  Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
• Add ChiselStage.emitCHIRRTLFile (backport #4232) (by @mergify[bot] in #4234)
  Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
• Make requireTypeEquivalent public and add context message (backport #4243) (by @mergify[bot] in #4247)
  Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
• Add map method for Valid (backport #4255) (by @mergify[bot] in #4258)
  Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
• Add more information when probe types don't match (backport #4269) (by @mergify[bot] in #4270)
  Add more information to the error message when attempting to probe.define to a mismatched chisel type.

API Deprecation

• Mark return value of .asTypeOf as "deprecated read-only" (backport #4198) (by @mergify[bot] in #4199)
  Previously, .asTypeOf would return a Wire. To get the old behavior, wrap the .asTypeOf call in WireInit(...).
• [LTL] Deprecate disable intrinsic (backport #4237) (by @mergify[bot] in #4239)

Performance

• Share ChildBinding objects between siblings (backport #4238) (by @mergify[bot] in #4241)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Move circuitVar from HasId to BaseModule (backport #4253) (by @mergify[bot] in #4263)
  • This removes a 4-byte field (8-bytes with heap > 32 GB) from all Data
• Optimize Record._elements to not duplicate VectorMap if possible (backport #4254) (by @mergify[bot] in #4265)
  This reduces memory use of a typical bundle by 20%.
• Remove autoSeedVar, use Boolean to distinguish suggested or autoSeed (backport #4252) (by @mergify[bot] in #4262)
  • Combined with #4251, reduces the memory use of a typical bound UInt from 64 bytes shallow, 120 bytes retained, to 56 bytes shallow, 112 bytes retained.
• Optimize .readOnly to only create views when necessary (backport #4271) (by @mergify[bot] in #4273)
• Share Node objects between siblings (backport #4259) (by @mergify[bot] in #4272)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Specialize Index for literal indices with LitIndex (backport #4268) (by @mergify[bot] in #4274)
  This saves 16-bytes per Vec element.

Fixes

• Suppress exception throwing in Data.toString (backport #4147) (by @mergify[bot] in #4153)
  This makes .toString behavior better outside of Chisel elaboration contexts.
• Error when calling define targeting a child of a probe (backport #4175) (by @mergify[bot] in #4176)
  This is already an error caught in firtool, now Chisel will error earlier.
• Support XMRs to Analog in D/I (backport #4181) (by @mergify[bot] in #4183)
• Distinguish identity views from single-target views (backport #4186) (by @mergify[bot] in #4189)
  Fixes #4185, Fixes #4187
• Initialize scala.util.control.NonFatal in Builder (backport #4195) (by @mergify[bot] in #4197)
• Fix BoringUtils for identity views (backport #4220) (by @mergify[bot] in #4221)
• Name the targets of identity views (backport #4222) (by @mergify[bot] in #4225)
• Make isView safe outside of Builder context (backport #4228) (by @mergify[bot] in #4231)
• Emit FIRRTL bulk connects even for "input" wires (backport #4219) (by @mergify[bot] in #4235)
• Use :<>= in VecInit methods instead of := or <> (backport #4248) (by @mergify[bot] in #4250)
  Previously, VecInit would try to "intelligently" select := or <> depending on if the type is bidirectional. :<>= has the desirable behavior here for both passive and bidirectional types. It also has the advantage over <> of handling internal wires.
• Fix .toString for dynamic indexing (backport #4260) (by @mergify[bot] in #4267)

Documentation

• Add a test for issue 4159 (backport #4161) (by @mergify[bot] in #4166)
• Add more exhaustive tests for .asTypeOf (backport #4160) (by @mergify[bot] in #4169)
• Fix import path in docstring (backport #4256) (by @mergify[bot] in #4257)

Build and Internal Changes

• [6.x] Enable MiMa for v6.4.0 (by @chiselbot in #4127)

Full Changelog: v6.4.0...v6.5.0