GitHub - freecores/ddr2_sdram: DDR2 SDRAM Controller

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
MIG_Settings		MIG_Settings
Testbench_DDR2		Testbench_DDR2
ipcore_dir/DDR2_Ram_Core/user_design		ipcore_dir/DDR2_Ram_Core/user_design
iseconfig		iseconfig
Buttons_VHDL.vhd		Buttons_VHDL.vhd
Clock_VHDL.vhd		Clock_VHDL.vhd
DDR2_Control_VHDL.vhd		DDR2_Control_VHDL.vhd
DDR2_Read_VHDL.vhd		DDR2_Read_VHDL.vhd
DDR2_Write_VHDL.vhd		DDR2_Write_VHDL.vhd
DDR2_liesmich.txt		DDR2_liesmich.txt
DDR2_readme.txt		DDR2_readme.txt
Prj12_Impact.ipf		Prj12_Impact.ipf
Prj_12_DDR2.gise		Prj_12_DDR2.gise
Prj_12_DDR2.xise		Prj_12_DDR2.xise
Top_Modul_VHDL.vhd		Top_Modul_VHDL.vhd
Top_Modul_VHDL_bitgen.xwbt		Top_Modul_VHDL_bitgen.xwbt
Top_Modul_VHDL_guide.ncd		Top_Modul_VHDL_guide.ncd
Top_Modul_VHDL_summary.html		Top_Modul_VHDL_summary.html
UB_Clock_UCF.ucf		UB_Clock_UCF.ucf
UB_Led_BUS_UCF.ucf		UB_Led_BUS_UCF.ucf
UB_Schalter_BUS_UCF.ucf		UB_Schalter_BUS_UCF.ucf
UB_Taster_BUS_UCF.ucf		UB_Taster_BUS_UCF.ucf
UB_Y-Led_UCF.ucf		UB_Y-Led_UCF.ucf
impact.xsl		impact.xsl
impact_impact.xwbt		impact_impact.xwbt
webtalk.log		webtalk.log
webtalk_impact.xml		webtalk_impact.xml