@freecores

FreeCores

A home for open source hardware cores

  • PS2 interface

    Verilog 3 2 Updated Dec 4, 2017
  • Mini-Risc core

    Verilog 5 Updated Dec 4, 2017
  • turbo 8051

    Verilog 6 6 Updated Aug 31, 2017
  • Freecores website

    CSS 11 3 Updated Dec 22, 2016
  • WISHBONE Builder

    Perl 7 2 Updated Sep 10, 2016
  • Simple RS232 UART

    Verilog 2 2 Updated Apr 3, 2016
  • AltOr32 - Alternative Lightweight OpenRisc CPU

    Verilog 4 7 LGPL-3.0 Updated Aug 10, 2014
  • No description

    C 1 Updated Jul 17, 2014
  • WB/OPB & OPB/WB Interface Wrapper

    Verilog 1 Updated Jul 18, 2014
  • LEM1_9

    VHDL 1 Updated Jul 17, 2014
  • AVR Core

    5 3 Updated Jul 18, 2014
  • ao486

    C++ 2 Updated Jul 18, 2014
  • FORTH processor with Java compiler

    Java 8 Updated Jul 17, 2014
  • ULA chip for ZX Spectrum

    Verilog 2 3 Updated Jul 17, 2014
  • ZPU - the worlds smallest 32 bit CPU with GCC toolchain

    VHDL 4 2 Updated Jul 17, 2014
  • Zorro bus to Wishbone bridge

    LGPL-2.1 Updated Jul 17, 2014
  • Zet - The x86 (IA-32) open implementation

    C 5 4 GPL-3.0 Updated Jul 17, 2014
  • ZBT SRAM Controller

    VHDL 1 1 Updated Jul 17, 2014
  • Z80 System on Chip

    VHDL 2 2 Updated Jul 17, 2014
  • z80control

    Pascal 1 1 Updated Jul 17, 2014
  • Yet Another VGA

    VHDL 1 1 BSD-3-Clause Updated Jul 17, 2014
  • Asynchronous WISHBONE-compatible SDRAM controller

    Verilog 1 2 Updated Jul 17, 2014
  • YACC-Yet Another CPU CPU

    Verilog 1 4 Updated Jul 17, 2014
  • YAC - Yet Another CORDIC Core

    VHDL 3 2 Updated Jul 17, 2014
  • Y80e - Z80/Z180 compatible processor extended by eZ80 instructions

    Verilog 1 5 Updated Jul 17, 2014
  • XTEA Core

    VHDL 1 2 Updated Jul 17, 2014
  • XTEA Crypto Core

    Verilog LGPL-2.1 Updated Jul 17, 2014
  • Xilinx Virtex FLoating Point

    Verilog 2 4 Updated Jul 17, 2014
  • Ethernet 10GE MAC

    Verilog 3 7 Updated Jul 17, 2014
  • Ethernet 10GE Low Latency MAC

    Objective-C 2 5 Updated Jul 17, 2014