FreeCores
A home for open source hardware cores
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Fixed Point Math Library for Verilog
Verilog
120
35
AXI DMA 32 / 64 bits
Verilog
98
33
Ethernet MAC 10/100 Mbps
Verilog
79
33
JPEG Encoder Verilog
Verilog
70
33
round robin arbiter
Verilog
67
22
Repositories
Showing 10 of 768 repositories
sc2v
Public
SystemC to Verilog Synthesizable Subset Translator
freecores/sc2v’s past year of commit activity
C
9
GPL-2.0
4
0
1
Updated May 12, 2023
i2c
Public
I2C controller core
freecores/i2c’s past year of commit activity
Verilog
33
36
2
2
Updated Jan 1, 2023
freecores/jpegencode’s past year of commit activity
Verilog
70
33
1
0
Updated Oct 31, 2022
xtea
Public
XTEA Crypto Core
freecores/xtea’s past year of commit activity
Verilog
3
LGPL-2.1
0
0
0
Updated Oct 31, 2022
des
Public
DES/Triple DES IP Cores
freecores/des’s past year of commit activity
Verilog
4
1
0
0
Updated Oct 30, 2022
freecores/aes_core’s past year of commit activity
Verilog
6
2
0
0
Updated Oct 30, 2022
freecores/tiny_aes’s past year of commit activity
Verilog
13
Apache-2.0
5
0
0
Updated Oct 4, 2022
embedded_risc
Public
Embedded 32-bit RISC uProcessor with SDRAM Controller
freecores/embedded_risc’s past year of commit activity
Verilog
24
6
0
0
Updated Sep 2, 2021
freecores/systemcmd5’s past year of commit activity
C++
4
5
0
0
Updated May 14, 2021
mmu180
Public
MMU for Z80 and eZ80
freecores/mmu180’s past year of commit activity
Verilog
15
3
0
0
Updated Mar 4, 2021
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