use coregen generated 32KB colour RAM instead of my GHDL-compatible

one to try to fix timing.

Makefile

@@ -71,7 +71,7 @@ transfer:	kickstart.vhdl version.vhdl kickstart65gs.bin makerom makeslowram ioma
 version.vhdl: version-template.vhdl version.sh .git/index *.vhdl *.vhd 
 	./version.sh
 
-SIMULATIONFILES=	viciv.vhdl cputypes.vhdl sid_voice.vhd sid_coeffs.vhd sid_filters.vhd sid_components.vhd version.vhdl kickstart.vhdl iomapper.vhdl container.vhd cpu_test.vhdl gs4510.vhdl UART_TX_CTRL.vhd uart_rx.vhdl uart_monitor.vhdl machine.vhdl cia6526.vhdl keymapper.vhdl ghdl_ram8x64k.vhdl charrom.vhdl ghdl_chipram8bit.vhdl ghdl_screen_ram_buffer.vhdl ghdl_ram9x4k.vhdl ghdl_ram18x2k.vhdl sdcardio.vhdl ghdl_ram8x512.vhdl ethernet.vhdl ramlatch64.vhdl shadowram.vhdl microcode.vhdl cputypes.vhdl version.vhdl sid_6581.vhd ghdl_ram128x1k.vhdl ghdl_ram8x4096.vhdl crc.vhdl slowram.vhdl framepacker.vhdl ghdl_videobuffer.vhdl vicii_sprites.vhdl sprite.vhdl ghdl_alpha_blend.vhdl ghdl_farstack.vhdl debugtools.vhdl
+SIMULATIONFILES=	viciv.vhdl cputypes.vhdl sid_voice.vhd sid_coeffs.vhd sid_filters.vhd sid_components.vhd version.vhdl kickstart.vhdl iomapper.vhdl container.vhd cpu_test.vhdl gs4510.vhdl UART_TX_CTRL.vhd uart_rx.vhdl uart_monitor.vhdl machine.vhdl cia6526.vhdl keymapper.vhdl ghdl_ram8x32k.vhdl charrom.vhdl ghdl_chipram8bit.vhdl ghdl_screen_ram_buffer.vhdl ghdl_ram9x4k.vhdl ghdl_ram18x2k.vhdl sdcardio.vhdl ghdl_ram8x512.vhdl ethernet.vhdl ramlatch64.vhdl shadowram.vhdl microcode.vhdl cputypes.vhdl version.vhdl sid_6581.vhd ghdl_ram128x1k.vhdl ghdl_ram8x4096.vhdl crc.vhdl slowram.vhdl framepacker.vhdl ghdl_videobuffer.vhdl vicii_sprites.vhdl sprite.vhdl ghdl_alpha_blend.vhdl ghdl_farstack.vhdl debugtools.vhdl
 simulate:	$(SIMULATIONFILES)
 	ghdl -i $(SIMULATIONFILES) 
 	ghdl -m cpu_test

c64accel.xise

@@ -78,7 +78,7 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
     </file>
-    <file xil_pn:name="ram8x64k.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="ram8x32k.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
     </file>
@@ -434,10 +434,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
     </file>
-    <file xil_pn:name="ghdl_ram8x64k.vhdl" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="163"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
-    </file>
   </files>
 
   <properties>

ghdl_ram8x64k.vhdl

@@ -24,7 +24,7 @@ END ram8x64k;
 
 architecture behavioural of ram8x64k is
 
-  type ram_t is array (0 to 32767) of std_logic_vector(7 downto 0);
+  type ram_t is array (0 to 65535) of std_logic_vector(7 downto 0);
   signal ram : ram_t := (
     0 => x"02", 1 => x"03", 2 => x"04", 3 => x"06", 4 => x"06", 5 => x"06", 6 => x"06", 7 => x"06", 8 => x"06", 39 => x"06",
     others => x"07");
@@ -36,15 +36,15 @@ begin  -- behavioural
 
   process(clka)
   begin
-    douta_drive <= ram(to_integer(unsigned(addra(14 downto 0))));
+    douta_drive <= ram(to_integer(unsigned(addra(15 downto 0))));
     douta <= douta_drive;
 
     --report "COLOURRAM: A Reading from $" & to_hstring(unsigned(addra))
     --  & " = $" & to_hstring(ram(to_integer(unsigned(addra))));
     if(rising_edge(Clka)) then 
       if ena='1' then
         if(wea="1") then
-          ram(to_integer(unsigned(addra(14 downto 0)))) <= dina;
+          ram(to_integer(unsigned(addra(15 downto 0)))) <= dina;
           report "COLOURRAM: A writing to $" & to_hstring(unsigned(addra))
             & " = $" & to_hstring(dina);
         end if;
@@ -54,7 +54,7 @@ begin  -- behavioural
 
   process (clkb,addrb,ram)
   begin
-    doutb_drive <= ram(to_integer(unsigned(addrb(14 downto 0))));
+    doutb_drive <= ram(to_integer(unsigned(addrb(15 downto 0))));
     doutb <= doutb_drive;
     if(rising_edge(Clkb)) then 
       if(web="1") then

ram8x32k.vhd

@@ -0,0 +1,161 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2015 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram8x32k.vhd when simulating
+-- the core, ram8x32k. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram8x32k IS
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END ram8x32k;
+
+ARCHITECTURE ram8x32k_a OF ram8x32k IS
+-- synthesis translate_off
+COMPONENT wrapped_ram8x32k
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+
+-- Configuration specification
+  FOR ALL : wrapped_ram8x32k USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+    GENERIC MAP (
+      c_addra_width => 15,
+      c_addrb_width => 15,
+      c_algorithm => 1,
+      c_axi_id_width => 4,
+      c_axi_slave_type => 0,
+      c_axi_type => 1,
+      c_byte_size => 9,
+      c_common_clk => 0,
+      c_default_data => "FF",
+      c_disable_warn_bhv_coll => 0,
+      c_disable_warn_bhv_range => 0,
+      c_enable_32bit_address => 0,
+      c_family => "artix7",
+      c_has_axi_id => 0,
+      c_has_ena => 1,
+      c_has_enb => 0,
+      c_has_injecterr => 0,
+      c_has_mem_output_regs_a => 0,
+      c_has_mem_output_regs_b => 0,
+      c_has_mux_output_regs_a => 0,
+      c_has_mux_output_regs_b => 0,
+      c_has_regcea => 0,
+      c_has_regceb => 0,
+      c_has_rsta => 0,
+      c_has_rstb => 0,
+      c_has_softecc_input_regs_a => 0,
+      c_has_softecc_output_regs_b => 0,
+      c_init_file => "BlankString",
+      c_init_file_name => "no_coe_file_loaded",
+      c_inita_val => "0",
+      c_initb_val => "0",
+      c_interface_type => 0,
+      c_load_init_file => 0,
+      c_mem_type => 2,
+      c_mux_pipeline_stages => 0,
+      c_prim_type => 1,
+      c_read_depth_a => 32768,
+      c_read_depth_b => 32768,
+      c_read_width_a => 8,
+      c_read_width_b => 8,
+      c_rst_priority_a => "CE",
+      c_rst_priority_b => "CE",
+      c_rst_type => "SYNC",
+      c_rstram_a => 0,
+      c_rstram_b => 0,
+      c_sim_collision_check => "ALL",
+      c_use_bram_block => 0,
+      c_use_byte_wea => 0,
+      c_use_byte_web => 0,
+      c_use_default_data => 1,
+      c_use_ecc => 0,
+      c_use_softecc => 0,
+      c_wea_width => 1,
+      c_web_width => 1,
+      c_write_depth_a => 32768,
+      c_write_depth_b => 32768,
+      c_write_mode_a => "WRITE_FIRST",
+      c_write_mode_b => "WRITE_FIRST",
+      c_write_width_a => 8,
+      c_write_width_b => 8,
+      c_xdevicefamily => "artix7"
+    );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram8x32k
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    douta => douta,
+    clkb => clkb,
+    web => web,
+    addrb => addrb,
+    dinb => dinb,
+    doutb => doutb
+  );
+-- synthesis translate_on
+
+END ram8x32k_a;

viciv.vhdl

@@ -204,8 +204,8 @@ architecture Behavioral of viciv is
           );
   end component charrom;
 
-  -- 64KB internal colour RAM
-  component ram8x64k IS
+  -- 32KB internal colour RAM
+  component ram8x32k IS
     PORT (
       clka : IN STD_LOGIC;
       ena : IN STD_LOGIC;
@@ -928,7 +928,7 @@ begin
 
   colourram: block
   begin
-  colourram1 : component ram8x64k
+  colourram1 : component ram8x32k
     PORT MAP (
       clka => cpuclock,
       ena => colour_ram_cs,