(Original readme for the template repository here)
(verilog flow from https://github.com/H-S-S-11/tinytapeout-verilog-test)
This design shows a simple LUTRAM cell, allowing the LUT configuration to be programmed via a traditional frame configuration (the shift register would be shared across the entire die, and the multi-bit frames loaded in parallel for each row/column of the configuration). Then at runtime a pulse generator and decoder enables the LUT also to be used as RAM.
The Verilog flow is:
- Fork this Repo
- Create a wokwi project to get an ID
- Update WOWKI_PROJECT_ID in Makefile
grep -rl "341154068332282450" ./src | sed -i "s/341154068332282450/YOUR_WOKWI_ID/g"
from the top of the repo to find and replace all occurences of the old ID insrc
with yours, and rename theuser_module
,user_module_tb
andscan_wrapper
files to use your ID- Replace behavioural code in user_module_ID.v with your own, likewise change the testbench
- Push changes, which triggers the GitHub Action to build the project