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Adding Vector Segmented Loads/Stores to RISC-V V 1.0 implementation #382

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ivanfv opened this issue Oct 2, 2023 · 3 comments
Closed

Adding Vector Segmented Loads/Stores to RISC-V V 1.0 implementation #382

ivanfv opened this issue Oct 2, 2023 · 3 comments
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@ivanfv
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arch-riscv The RISC-V ISA

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@ivanfv
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ivanfv commented Oct 2, 2023

Hello,

I am opening this issue to ask if someone is working on the Vector Segmented Loads/Stores to the RISC-V Vector 1.0 implementation (e.g., vlseg, vsseg), which, if I am not wrong, are not supported by gem5 yet.

For the moment being, I am checking 1) how LD2, LD3 and LD4 Arm's instructions are implemented and 2) how vector register gather could help.

I will report the advances over here once I have significant progress.

Best,
Ivan

CC @adriaarmejach
@BobbyRBruce BobbyRBruce added the arch-riscv The RISC-V ISA label Oct 3, 2023
@BobbyRBruce BobbyRBruce assigned BobbyRBruce and ivanfv and unassigned BobbyRBruce Oct 3, 2023
@ivanfv ivanfv mentioned this issue Nov 28, 2023
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@ivanaamit
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Hi @ivanfv, I'm just checking to see the status of this issue. Are you currently working on it? Thanks.

@ivanfv
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ivanfv commented Jan 9, 2024

Hi @ivanaamit , yes, I am working on this. Currently, I am validating the vector segmented loads implementation and I plan to create a pull request about them very soon. Thanks for checking this!

ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 5, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
5071681 
This commit adds support for vector segmented unit-stride segment load operations
for RISC-V vlseg<NF>e<X>. This implementation is based in two types of microops:
- VlSeg uops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv uops that properly deinterleave structs into destination registers.

Gem5 issue: gem5#382
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 5, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
488ddf2 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg uops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv uops that properly deinterleave structs into destination registers.

Gem5 issue: gem5#382
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 5, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
86e705c 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Gem5 issue: gem5#382
@ivanfv ivanfv mentioned this issue Feb 5, 2024
Merged
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 6, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
25529c7 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 7, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
17abe0b 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97

Update src/arch/riscv/insts/vector.hh

Change tmp_d0 to reference type

Co-authored-by: Yu-Cheng Chang <aucixw45876@gmail.com>

implemting fixes

Change-Id: I5cd4ee2d13bddb9f3ae5e9c9920e58baff0717b6
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 7, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
94e6776 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97

Update src/arch/riscv/insts/vector.hh

Change tmp_d0 to reference type

Co-authored-by: Yu-Cheng Chang <aucixw45876@gmail.com>

implemting fixes

Change-Id: I5cd4ee2d13bddb9f3ae5e9c9920e58baff0717b6
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 7, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
e9ef3b8 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97

Update src/arch/riscv/insts/vector.hh

Change tmp_d0 to reference type

Co-authored-by: Yu-Cheng Chang <aucixw45876@gmail.com>

implemting fixes

Change-Id: I5cd4ee2d13bddb9f3ae5e9c9920e58baff0717b6
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 9, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
859f38e 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 9, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
b8086fc 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 9, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
4c71e24 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 9, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
6c77374 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 9, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
fb0e960 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 12, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
182a653 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 12, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
007ba30 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 13, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
a0009e3 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 13, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
44beb77 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 14, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
d3bd257 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 14, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
8b72b8b 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 19, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
9717cd7 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 20, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
d6bc124 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 21, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
3a12431 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 22, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
149ae27 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
ivanfv added a commit to ivanfv/gem5 that referenced this issue Feb 26, 2024
@ivanfv
arch-riscv: This commit adds vector unit-stride segment loads to RISC-V
c2a1737 
This commit adds support for vector unit-stride segment load operations for
RISC-V (vlseg<NF>e<X>). This implementation is based in two types of microops:
- VlSeg microops that load data as it is organized in memory in structs of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into destination registers.

Issue: gem5#382

Change-Id: Iaba96d9000f244e824d89089a4f09b42ec130f97
@ivanfv ivanfv mentioned this issue Mar 5, 2024
Merged
ivanaamit pushed a commit that referenced this issue Mar 6, 2024
@ivanfv
arch-riscv: adding vector unit-stride segment loads to RISC-V (#851)
f6c6183 
This commit adds support for vector unit-stride segment load operations
for RISC-V (vlseg<NF>e<X>). This implementation is based in two types of
microops:
- VlSeg microops that load data as it is organized in memory in structs
of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into
destination registers.

Gem5 issue: #382
powerjg pushed a commit that referenced this issue Mar 22, 2024
@ivanfv
arch-riscv: adding vector unit-stride segment stores to RISC-V (#913)
1e743fd 
This commit adds support for vector unit-stride segment store operations
for RISC-V (vssegXeXX). This implementation is based in two types of
microops:
- VsSegIntrlv microops that properly interleave source registers into
structs.
- VsSeg microops that store data in memory as contiguous structs of
several fields.

Change-Id: Id80dd4e781743a60eb76c18b6a28061f8e9f723d

Gem5 issue: #382
BobbyRBruce pushed a commit to BobbyRBruce/gem5 that referenced this issue Mar 26, 2024
@ivanfv @BobbyRBruce
arch-riscv: adding vector unit-stride segment stores to RISC-V (gem5#913
bf64b6e 
)

This commit adds support for vector unit-stride segment store operations
for RISC-V (vssegXeXX). This implementation is based in two types of
microops:
- VsSegIntrlv microops that properly interleave source registers into
structs.
- VsSeg microops that store data in memory as contiguous structs of
several fields.

Change-Id: Id80dd4e781743a60eb76c18b6a28061f8e9f723d

Gem5 issue: gem5#382
@ivanaamit
Copy link
Contributor

Since #851 and #913 have been merged, I am closing this issue. @ivanfv, please reopen it if I am mistaken. Thanks.

BobbyRBruce pushed a commit to BobbyRBruce/gem5 that referenced this issue Mar 26, 2024
@ivanfv @BobbyRBruce
arch-riscv: adding vector unit-stride segment stores to RISC-V (gem5#913
7f26013 
)

This commit adds support for vector unit-stride segment store operations
for RISC-V (vssegXeXX). This implementation is based in two types of
microops:
- VsSegIntrlv microops that properly interleave source registers into
structs.
- VsSeg microops that store data in memory as contiguous structs of
several fields.

Change-Id: Id80dd4e781743a60eb76c18b6a28061f8e9f723d

Gem5 issue: gem5#382
BobbyRBruce pushed a commit to BobbyRBruce/gem5 that referenced this issue Mar 30, 2024
@ivanfv @BobbyRBruce
arch-riscv: adding vector unit-stride segment stores to RISC-V (gem5#913
05b601c 
)

This commit adds support for vector unit-stride segment store operations
for RISC-V (vssegXeXX). This implementation is based in two types of
microops:
- VsSegIntrlv microops that properly interleave source registers into
structs.
- VsSeg microops that store data in memory as contiguous structs of
several fields.

Change-Id: Id80dd4e781743a60eb76c18b6a28061f8e9f723d

Gem5 issue: gem5#382
mjkpolo pushed a commit to mjkpolo/gem5 that referenced this issue Apr 15, 2024
@ivanfv @mjkpolo
arch-riscv: adding vector unit-stride segment loads to RISC-V (gem5#851)
f29b190 
This commit adds support for vector unit-stride segment load operations
for RISC-V (vlseg<NF>e<X>). This implementation is based in two types of
microops:
- VlSeg microops that load data as it is organized in memory in structs
of several fields.
- VectorDeIntrlv microops that properly deinterleave structs into
destination registers.

Gem5 issue: gem5#382
mjkpolo pushed a commit to mjkpolo/gem5 that referenced this issue Apr 15, 2024
@ivanfv @mjkpolo
arch-riscv: adding vector unit-stride segment stores to RISC-V (gem5#913
94a789e 
)

This commit adds support for vector unit-stride segment store operations
for RISC-V (vssegXeXX). This implementation is based in two types of
microops:
- VsSegIntrlv microops that properly interleave source registers into
structs.
- VsSeg microops that store data in memory as contiguous structs of
several fields.

Change-Id: Id80dd4e781743a60eb76c18b6a28061f8e9f723d

Gem5 issue: gem5#382
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