mem-ruby, configs: Add a generic CHI controller as a stepping stone for ruby+classic topology

configs/ruby/CHI.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2021 ARM Limited
+# Copyright (c) 2021, 2024 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -102,32 +102,6 @@ def create_system(
     CHI_RNI_DMA = chi_defs.CHI_RNI_DMA
     CHI_RNI_IO = chi_defs.CHI_RNI_IO
 
-    # Declare caches and controller types used by the protocol
-    # Notice tag and data accesses are not concurrent, so the a cache hit
-    # latency = tag + data + response latencies.
-    # Default response latencies are 1 cy for all controllers.
-    # For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
-    # this is deducted from the initial tag read latency for sequencer requests
-    # dataAccessLatency may be set to 0 if one wants to consider parallel
-    # data and tag lookups
-    class L1ICache(RubyCache):
-        dataAccessLatency = 1
-        tagAccessLatency = 1
-        size = options.l1i_size
-        assoc = options.l1i_assoc
-
-    class L1DCache(RubyCache):
-        dataAccessLatency = 2
-        tagAccessLatency = 1
-        size = options.l1d_size
-        assoc = options.l1d_assoc
-
-    class L2Cache(RubyCache):
-        dataAccessLatency = 6
-        tagAccessLatency = 2
-        size = options.l2_size
-        assoc = options.l2_assoc
-
     class HNFCache(RubyCache):
         dataAccessLatency = 10
         tagAccessLatency = 2
@@ -147,25 +121,23 @@ class HNFCache(RubyCache):
 
     # Creates on RNF per cpu with priv l2 caches
     assert len(cpus) == options.num_cpus
-    ruby_system.rnf = [
-        CHI_RNF(
-            [cpu],
-            ruby_system,
-            L1ICache,
-            L1DCache,
-            system.cache_line_size.value,
-        )
-        for cpu in cpus
-    ]
+
+    rnf_cb = getattr(system, "_rnf_gen", CHI_RNF.generate)
+
+    # Generate the Request Nodes
+    ruby_system.rnf = rnf_cb(options, ruby_system, cpus)
+
     for rnf in ruby_system.rnf:
-        rnf.addPrivL2Cache(L2Cache)
         cpu_sequencers.extend(rnf.getSequencers())
         all_cntrls.extend(rnf.getAllControllers())
         network_nodes.append(rnf)
         network_cntrls.extend(rnf.getNetworkSideControllers())
 
-    # Creates one Misc Node
-    ruby_system.mn = [CHI_MN(ruby_system, [cpu.l1d for cpu in cpus])]
+    mn_cb = getattr(system, "_mn_gen", CHI_MN.generate)
+
+    # Generate the Misc Nodes
+    ruby_system.mn = mn_cb(options, ruby_system, cpus)
+
     for mn in ruby_system.mn:
         all_cntrls.extend(mn.getAllControllers())
         network_nodes.append(mn)

configs/ruby/CHI_config.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2021-2023 ARM Limited
+# Copyright (c) 2021-2024 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -51,6 +51,29 @@
 from m5.objects import *
 
 
+# Declare caches and controller types used by the protocol
+# Notice tag and data accesses are not concurrent, so the a cache hit
+# latency = tag + data + response latencies.
+# Default response latencies are 1 cy for all controllers.
+# For L1 controllers the mandatoryQueue enqueue latency is always 1 cy and
+# this is deducted from the initial tag read latency for sequencer requests
+# dataAccessLatency may be set to 0 if one wants to consider parallel
+# data and tag lookups
+class L1ICache(RubyCache):
+    dataAccessLatency = 1
+    tagAccessLatency = 1
+
+
+class L1DCache(RubyCache):
+    dataAccessLatency = 2
+    tagAccessLatency = 1
+
+
+class L2Cache(RubyCache):
+    dataAccessLatency = 6
+    tagAccessLatency = 2
+
+
 class Versions:
     """
     Helper class to obtain unique ids for a given controller class.
@@ -575,6 +598,24 @@ def addPrivL2Cache(self, cache_type, pf_type=None):
                 c.downstream_destinations = [cpu.l2]
             cpu._ll_cntrls = [cpu.l2]
 
+    @classmethod
+    def generate(cls, options, ruby_system, cpus):
+        rnfs = [
+            CHI_RNF(
+                [cpu],
+                ruby_system,
+                L1ICache(size=options.l1i_size, assoc=options.l1i_assoc),
+                L1DCache(size=options.l1d_size, assoc=options.l1d_assoc),
+                options.cacheline_size,
+            )
+            for cpu in cpus
+        ]
+        for rnf in rnfs:
+            rnf.addPrivL2Cache(
+                L2Cache(size=options.l2_size, assoc=options.l2_assoc)
+            )
+        return rnfs
+
 
 class CHI_HNF(CHI_Node):
     """
@@ -678,6 +719,13 @@ def getAllControllers(self):
     def getNetworkSideControllers(self):
         return [self._cntrl]
 
+    @classmethod
+    def generate(cls, options, ruby_system, cpus):
+        """
+        Creates one Misc Node
+        """
+        return [CHI_MN(ruby_system, [cpu.l1d for cpu in cpus])]
+
 
 class CHI_SNF_Base(CHI_Node):
     """

src/mem/ruby/protocol/chi/CHI-cache-actions.sm

@@ -1884,6 +1884,7 @@ action(Send_SnpSharedFwd_ToOwner, desc="") {
     if (retToSrc) {
       tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_SC_Fwded_SC);
       tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_SC_Fwded_SD_PD);
+      tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_SD_Fwded_SC);
       tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_I_Fwded_SC);
       tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_I_Fwded_SD_PD);
     } else {
@@ -1898,6 +1899,7 @@ action(Send_SnpSharedFwd_ToOwner, desc="") {
       tbe.expected_snp_resp.addExpectedRespType(CHIResponseType:SnpResp_SC_Fwded_SC);
     }
     tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_SC_PD_Fwded_SC);
+    tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_SD_Fwded_SC);
     tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_I_PD_Fwded_SC);
   }
   tbe.expected_snp_resp.addExpectedCount(1);
@@ -1927,6 +1929,7 @@ action(Send_SnpSharedFwd_ToSharer, desc="") {
   bool retToSrc := tbe.doCacheFill;
   if (retToSrc) {
     tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_SC_Fwded_SC);
+    tbe.expected_snp_resp.addExpectedDataType(CHIDataType:SnpRespData_I_Fwded_SC);
   } else {
     tbe.expected_snp_resp.addExpectedRespType(CHIResponseType:SnpResp_SC_Fwded_SC);
   }
@@ -2234,7 +2237,8 @@ action(UpdateDirState_FromSnpDataResp, desc="") {
                  (in_msg.type == CHIDataType:SnpRespData_SC) ||
                  (in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SC) ||
                  (in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SD_PD) ||
-                 (in_msg.type == CHIDataType:SnpRespData_SC_PD_Fwded_SC)) {
+                 (in_msg.type == CHIDataType:SnpRespData_SC_PD_Fwded_SC) ||
+                 (in_msg.type == CHIDataType:SnpRespData_SD_Fwded_SC)) {
         // the owner must have been the responder, if there was one
         assert((tbe.dir_ownerExists == false) ||
              (tbe.dir_ownerExists && (tbe.dir_owner == in_msg.responder)));
@@ -2243,12 +2247,16 @@ action(UpdateDirState_FromSnpDataResp, desc="") {
         tbe.dir_ownerIsExcl := false;
         if ((in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SC) ||
             (in_msg.type == CHIDataType:SnpRespData_SC_PD_Fwded_SC) ||
-            (in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SD_PD)) {
+            (in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SD_PD) ||
+            (in_msg.type == CHIDataType:SnpRespData_SD_Fwded_SC)) {
           tbe.dir_sharers.add(tbe.requestor);
         }
         if (in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SD_PD) {
           tbe.dir_ownerExists := true;
           tbe.dir_owner := tbe.requestor;
+        } else if (in_msg.type == CHIDataType:SnpRespData_SD_Fwded_SC) {
+          tbe.dir_ownerExists := true;
+          tbe.dir_owner := in_msg.responder;
         }
 
       } else if ((in_msg.type == CHIDataType:SnpRespData_I_Fwded_SD_PD) ||
@@ -2437,7 +2445,8 @@ action(UpdateDataState_FromSnpDataResp, desc="") {
 
       } else if ((in_msg.type == CHIDataType:SnpRespData_SD) ||
                  (in_msg.type == CHIDataType:SnpRespData_SC_Fwded_SD_PD) ||
-                 (in_msg.type == CHIDataType:SnpRespData_I_Fwded_SD_PD)) {
+                 (in_msg.type == CHIDataType:SnpRespData_I_Fwded_SD_PD) ||
+                 (in_msg.type == CHIDataType:SnpRespData_SD_Fwded_SC)) {
         tbe.dataDirty := true;
         tbe.dataValid := true;
         tbe.dataMaybeDirtyUpstream := true;

src/mem/ruby/protocol/chi/CHI-cache-funcs.sm

@@ -228,6 +228,7 @@ void functionalRead(Addr addr, Packet *pkt, WriteMask &mask) {
             tbe.expected_snp_resp.receivedDataType(CHIDataType:SnpRespData_UD) ||
             tbe.expected_snp_resp.receivedDataType(CHIDataType:SnpRespData_SC_Fwded_SD_PD) ||
             tbe.expected_snp_resp.receivedDataType(CHIDataType:SnpRespData_SC_PD_Fwded_SC) ||
+            tbe.expected_snp_resp.receivedDataType(CHIDataType:SnpRespData_SD_Fwded_SC) ||
             tbe.expected_snp_resp.receivedDataType(CHIDataType:SnpRespData_I_Fwded_SD_PD) ||
             tbe.expected_snp_resp.receivedDataType(CHIDataType:SnpRespData_I_PD_Fwded_SC);
     }
@@ -1412,6 +1413,8 @@ Event dataToEvent (CHIDataType type) {
     return Event:SnpRespData_SC_Fwded_SC;
   } else if (type == CHIDataType:SnpRespData_SC_Fwded_SD_PD) {
     return Event:SnpRespData_SC_Fwded_SD_PD;
+  } else if (type == CHIDataType:SnpRespData_SD_Fwded_SC) {
+    return Event:SnpRespData_SD_Fwded_SC;
   } else if (type == CHIDataType:SnpRespData_SC_PD_Fwded_SC) {
     return Event:SnpRespData_SC_PD_Fwded_SC;
   } else if (type == CHIDataType:SnpRespData_I_Fwded_SD_PD) {

src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

@@ -1389,6 +1389,7 @@ transition(BUSY_BLKD,
            {SnpRespData_I_PD,SnpRespData_I,SnpRespData_SC_PD,
             SnpRespData_SC,SnpRespData_SD,SnpRespData_UC,SnpRespData_UD,
             SnpRespData_SC_Fwded_SC,SnpRespData_SC_Fwded_SD_PD,
+            SnpRespData_SD_Fwded_SC,
             SnpRespData_SC_PD_Fwded_SC,SnpRespData_I_Fwded_SD_PD,
             SnpRespData_I_PD_Fwded_SC,SnpRespData_I_Fwded_SC}) {
   Receive_SnpDataResp;

src/mem/ruby/protocol/chi/CHI-cache.sm

@@ -405,6 +405,7 @@ machine(MachineType:Cache, "Cache coherency protocol") :
     SnpRespData_UD,                desc="";
     SnpRespData_SC_Fwded_SC,       desc="";
     SnpRespData_SC_Fwded_SD_PD,    desc="";
+    SnpRespData_SD_Fwded_SC,       desc="";
     SnpRespData_SC_PD_Fwded_SC,    desc="";
     SnpRespData_I_Fwded_SD_PD,     desc="";
     SnpRespData_I_PD_Fwded_SC,     desc="";

src/mem/ruby/protocol/chi/CHI-msg.sm

@@ -202,6 +202,7 @@ enumeration(CHIDataType, desc="...") {
   SnpRespData_SC_Fwded_SC;
   SnpRespData_SC_Fwded_SD_PD;
   SnpRespData_SC_PD_Fwded_SC;
+  SnpRespData_SD_Fwded_SC;
   SnpRespData_I_Fwded_SD_PD;
   SnpRespData_I_PD_Fwded_SC;
   SnpRespData_I_Fwded_SC;
@@ -240,6 +241,7 @@ structure(CHIDataMsg, desc="", interface="Message") {
                     (type == CHIDataType:SnpRespData_SD) ||
                     (type == CHIDataType:SnpRespData_UD) ||
                     (type == CHIDataType:SnpRespData_SC_Fwded_SD_PD) ||
+                    (type == CHIDataType:SnpRespData_SD_Fwded_SC) ||
                     (type == CHIDataType:SnpRespData_SC_PD_Fwded_SC) ||
                     (type == CHIDataType:SnpRespData_I_Fwded_SD_PD) ||
                     (type == CHIDataType:SnpRespData_I_PD_Fwded_SC);

src/mem/ruby/protocol/chi/generic/CHIGeneric.py

@@ -0,0 +1,55 @@
+# Copyright (c) 2023 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Controller import RubyController
+from m5.params import *
+
+
+class CHIGenericController(RubyController):
+    type = "CHIGenericController"
+    cxx_header = "mem/ruby/protocol/chi/generic/CHIGenericController.hh"
+    cxx_class = "gem5::ruby::CHIGenericController"
+    abstract = True
+
+    data_channel_size = Param.Int("")
+
+    reqOut = Param.MessageBuffer("")
+    snpOut = Param.MessageBuffer("")
+    rspOut = Param.MessageBuffer("")
+    datOut = Param.MessageBuffer("")
+    reqIn = Param.MessageBuffer("")
+    snpIn = Param.MessageBuffer("")
+    rspIn = Param.MessageBuffer("")
+    datIn = Param.MessageBuffer("")