arch-riscv: Fix c.jalr and c.jr instruction

[rogerchang23424]

The bit 0 of register should be 0 for jump address. Wrong handling the jump address may cause infinite run or segment fault.

gem5 issue: #981
Change-Id: I605de64bd3cece70288ffcfaf1f4263c17ab2971

[hnpl]

The code looks good to me.

I'm not sure if the riscv-related tests we have contain those instructions. Can you let me know if the code has been tested?

[rogerchang23424]

I have tested them with riscof. However, the case doesn't included in the riscof, so I add them to test case riscv-non-isa/riscv-arch-test#466.

Since we can't dump the memory signature directly with gem5. Instead, I compared the signature with customized plugin (gem5/gem5-resources#7) with other simulators.

[hnpl]

That's great!!