arch,cpu,sim: Add mechanism to partially print vector regs #1234
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I tested this change set by producing the traces from a simple RVV binary with and without this change set. The desired outcome is to only have differences in the amount of vector register content printed by the tracer. It looks like the output matches the expected outcome.
I'll test this change with SVE binaries and probably some x86 binaries with SSE* instructions. I also tested this change set by compiling |
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DataStatus is used by InstTracer to determine the data format of the content of the destination register of an instruction. The types consists of integer types (`DataInt*`), a floating point type (`DataDouble`), and a vector type (`DataReg`). Currently, the `setData(RegClass, *)` function assumes the register value to be of type `DataReg`, which means the content of the register is an array of values, for every `RegClass`. However, there are cases in the ISA implementation that the `setData` function above is used for writing an integer to the trace. This change addresses this issue by setting DataStatus accordingly to RegClass. Change-Id: I79423a4942ab2a3fde5c9cf86de0d1fced648cf0 Signed-off-by: Hoa Nguyen <hn@hnpl.org>
Vector-length Agnostic (VLA) is a style of vectorization in which the vectorized code can run on any vector length implemented by the microarchitecture. This vectorization style appears in SVE/SVE2 (an extension of ARM ISA) and RVV (an extension of RISC-V ISA). This change adds a function to the gem5's ISA interface returning the vector length of the VLA registers. For ARM ISA, it returns SVE_VL. For RISC-V ISA, it returns VLEN. For other ISAs, it returns -1. Change-Id: I8e622c9ab47a36770479c0ff68a15522602c82bf Signed-off-by: Hoa Nguyen <hn@hnpl.org>
Currently, gem5's inst tracer prints the whole vector register container by default. The size of vector register containers in gem5 is the maximum size allowed by the ISA. For vector-length agnostic (VLA) vector registers, this means ARM SVE vector container is 2048 bits long, and RISC-V vector container is 65535 bits long. Note that VLA implementation in gem5 allows the vector length to be varied within the limit specified by the ISAs. However, in most use cases of gem5, the vector length is much less than 65535 bits. This causes two issues: (1) the vector container requires allocating and moving around a large amount of unused data while only a fraction of it is used, and (2) printing the execution trace of a vector register results in a wall of text with a small amount of useful data. This change addresses the problem (2) by providing a mechanism to limit the amount data printed by the instruction tracer. This is done by adding an function printing the first X bits of a vector register container, where X is the vector length determined at runtime, as opposed to the vector container size, which is determined at compilation time. Change-Id: I815fa5aa738373510afcfb0d544a5b19c40dc0c7 Signed-off-by: Hoa Nguyen <hn@hnpl.org>
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It seems to work properly with SVE instructions.
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hnpl
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Jun 14, 2024
| dataStatus = DataReg; | ||
| switch (reg_class.type()) { | ||
| case IntRegClass: | ||
| case MiscRegClass: |
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I'm not really confident about this part. I'm not entirely sure that MiscRegs and CCRegs are always not larger than 64 bits.
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I just realized that the x86 instructions modifying xmm registers are broken down into micro-ops and do not need the vector container printing method. So the SSE* instructions will have the same trace as before. |
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Currently, gem5's inst tracer prints the whole vector register container by default. The size of vector register containers in gem5 is the maximum size allowed by the ISA. For vector-length agnostic (VLA) vector registers, this means ARM SVE vector container is 2048 bits long, and RISC-V vector container is 65535 bits long. Note that VLA implementation in gem5 allows the vector length to be varied within the limit specified by the ISAs.
However, in most use cases of gem5, the vector length is much less than 65535 bits. This causes two issues: (1) the vector container requires allocating and moving around a large amount of unused data while only a fraction of it is used, and (2) printing the execution trace of a vector register results in a wall of text with a small amount of useful data.
This change addresses the problem (2) by providing a mechanism to limit the amount data printed by the instruction tracer. This is done by adding a function printing the first X bits of a vector register container, where X is the vector length determined at runtime, as opposed to the vector container size, which is determined at compilation time.
Change-Id: I815fa5aa738373510afcfb0d544a5b19c40dc0c7