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arch-riscv: Relation chain on RVV support #83

Merged
merged 8 commits into from
Aug 3, 2023
Merged

arch-riscv: Relation chain on RVV support #83

merged 8 commits into from
Aug 3, 2023

Commits on Aug 2, 2023

  1. arch-riscv: Add risc-v vector regs and configs 

    This commit add regs and configs for vector extension

* Add 32 vector arch regs as spec defined and 8 internal regs for
  uop-based vector implementation.
* Add default vector configs(VLEN = 256, ELEN = 64). These cannot
  be changed yet, since the vector implementation has only be tested
  with such configs.
* Add disassamble register name v0~v31 and vtmp0~vtmp7.
* Add CSR registers defined in RISCV Vector Spec v1.0.
* Add vector bitfields.
* Add vector operand_types and operands.

Change-Id: I7bbab1ee9e0aa804d6f15ef7b77fac22d4f7212a
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Co-authored-by: Jerin Joy <joy@rivosinc.com>

arch-riscv: enable rvv flags only for RV64

Change-Id: I6586e322dfd562b598f63a18964d17326c14d4cf
    @huxuan0307 @adriaarmejach
    huxuan0307 authored and adriaarmejach committed Aug 2, 2023
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  2. arch-riscv: Add risc-v vector ext v1.0 vset insts support 

    Change-Id: I84363164ca327151101e8a1c3d8441a66338c909
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>

arch-riscv: Add a todo to fix vsetvl stall on decode

Change-Id: Iafb129648fba89009345f0c0ad3710f773379bf6
    @huxuan0307 @adriaarmejach
    huxuan0307 authored and adriaarmejach committed Aug 2, 2023
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  3. arch-riscv: Add risc-v vector ext v1.0 mem insts support 

    * TODOs:
  + Vector Segment Load/Store
  + Vector Fault-only-first Load

Change-Id: I2815c76404e62babab7e9466e4ea33ea87e66e75
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Co-authored-by: Jerin Joy <joy@rivosinc.com>
    @huxuan0307 @ksco
    @FanYang98 @jerinjoy @adriaarmejach
    4 people authored and adriaarmejach committed Aug 2, 2023
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  4. arch-riscv: Add risc-v vector ext v1.0 arith insts support 

    TODOs:
  + vcompress.vm

Change-Id: I86eceae66e90380416fd3be2c10ad616512b5eba
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Co-authored-by: Jerin Joy <joy@rivosinc.com>

arch-riscv: Add LICENCE to template files

Change-Id: I825e72bffb84cce559d2e4c1fc2246c3b05a1243
    @huxuan0307 @adriaarmejach
    huxuan0307 authored and adriaarmejach committed Aug 2, 2023
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  5. configs: update riscv restore checkpoint test 

    Change-Id: I019fc6394a03196711ab52533ad8062b22c89daf
    @adriaarmejach
    adriaarmejach committed Aug 2, 2023
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  6. arch-riscv: Add fatal if RVV used with o3 or minor 

    Since the O3 and Minor CPU models do not support RVV right now as the
implementation stalls the decode until vsetvl instructions are exectued,
this change calls `fatal` if RVV is not explicitly enabled.

It is possible to override this if you explicitly enable RVV in the
config file.

Change-Id: Ia801911141bb2fb2bedcff3e139bf41ba8936085
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
    @powerjg @adriaarmejach
    powerjg authored and adriaarmejach committed Aug 2, 2023
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  7. arch-riscv: Improve style 

    Minor style fixes in vector code

Change-Id: If0de45a2dbfb5d5aaa65ed3b5d91d9bee9bcc960
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
    @powerjg @adriaarmejach
    powerjg authored and adriaarmejach committed Aug 2, 2023
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  8. arch-riscv: Make vset*vl* instructions serialize 

    Current implementation of vset*vl* instructions serialize pipeline and
are non-speculative.

Change-Id: Ibf93b60133fb3340690b126db12827e36e2c202d
    @adriaarmejach
    adriaarmejach committed Aug 2, 2023
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