fixup "hw: introduction of cpu local mem area" (migv)

Issue genodelabs/genode#5310
genodelabs · Aug 1, 2024 · c5ffe94 · c5ffe94
1 parent cae85d8
commit c5ffe94
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Showing 2 changed files with 4 additions and 5 deletions.
diff --git a/lib/mk/spec/riscv/bootstrap-hw-migv.mk b/lib/mk/spec/riscv/bootstrap-hw-migv.mk
@@ -1,10 +1,10 @@
 INC_DIR += $(REP_DIR)/src/bootstrap/board/migv
 
-SRC_S   += bootstrap/spec/riscv/crt0.s
+SRC_CC  += bootstrap/platform_cpu_memory_area.cc
 SRC_CC  += bootstrap/spec/riscv/platform.cc
+SRC_S   += bootstrap/spec/riscv/crt0.s
 SRC_CC  += lib/base/riscv/kernel/interface.cc
-SRC_CC  += spec/64bit/memory_map.cc
 
-vpath spec/64bit/memory_map.cc $(call select_from_repositories,/src/lib/hw)
+ARCH_WIDTH_PATH := spec/64bit
 
 include $(call select_from_repositories,lib/mk/bootstrap-hw.inc)
diff --git a/lib/mk/spec/riscv/core-hw-migv.mk b/lib/mk/spec/riscv/core-hw-migv.mk
@@ -15,13 +15,12 @@ SRC_CC += spec/riscv/kernel/pd.cc
 SRC_CC += spec/riscv/cpu.cc
 SRC_CC += spec/riscv/pic.cc
 SRC_CC += spec/riscv/platform_support.cc
-SRC_CC += spec/64bit/memory_map.cc
 
 #add assembly sources
 SRC_S += spec/riscv/exception_vector.s
 SRC_S += spec/riscv/crt0.s
 
-vpath spec/64bit/memory_map.cc $(call select_from_repositories,/src/lib/hw)
+ARCH_WIDTH_PATH := spec/64bit
 vpath board/migv/timer.cc $(REP_DIR)/src/core
 
 # include less specific configuration