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library IEEE; | ||
use IEEE.std_logic_1164.all; | ||
use IEEE.numeric_std.all; | ||
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entity ent is | ||
generic ( | ||
W : integer := 1 | ||
); | ||
port ( | ||
wen : in std_logic_vector(W-1 downto 0) | ||
); | ||
end entity ent; | ||
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architecture rtl of ent is | ||
begin | ||
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process begin | ||
report "Hello world from ent." severity note; | ||
wait; | ||
end process; | ||
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end rtl; |
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#! /bin/sh | ||
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. ../../testenv.sh | ||
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export GHDL_STD_FLAGS=--std=08 | ||
analyze ent.vhdl top.vhdl | ||
elab_simulate top | ||
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clean | ||
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echo "Test successful" |
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library IEEE; | ||
use IEEE.std_logic_1164.all; | ||
use IEEE.numeric_std.all; | ||
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entity top is | ||
generic ( | ||
W : integer := 1 | ||
); | ||
end entity top; | ||
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architecture rtl of top is | ||
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signal write : std_logic; | ||
-- workaround | ||
signal wen : std_logic_vector(W-1 downto 0); | ||
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begin | ||
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process begin | ||
report "Hello world from top" severity note; | ||
wait; | ||
end process; | ||
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write <= '0'; | ||
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-- workaround | ||
wen <= (others => write); | ||
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u_ent: entity work.ent | ||
generic map( | ||
W => W | ||
) | ||
port map( | ||
-- workaround | ||
wen => (others => write) | ||
-- wen => wen | ||
); | ||
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end rtl; |