doc: announce v1.0 (#1840)

* doc: fix old refs to readthedocs

* doc/news: v1.0 announcement

NEWS.md

@@ -1,4 +1,17 @@
-**1.0-dev** (XXXX-XX-XX)
+**2.0-dev** (XXXX-XX-XX)
+
+**1.0** (2021-02-02)
+
+- Plugin for Yosys moved from [tgingold/ghdlsynth-beta](https://github.com/tgingold/ghdlsynth-beta) to [ghdl/ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin).
+- Python bindings overhauled and renamed to `pyGHDL`. Three modules are included: `libghdl`, `lsp` and `dom`.
+- The utility scripts in the codebase moved into subdir `scripts`: CI, binding generation, vendors, etc.
+- Repository [ghdl/ghdl-cosim](https://github.com/ghdl/ghdl-cosim) created. It contains documentation and code examples related to VHPIDIRECT, VPI and SystemC.
+- Repository [ghdl/extended-tests](https://github.com/ghdl/extended-tests) created for testing `vendors` build scripts.
+- GitHub Action [ghdl/setup-ghdl-ci](https://github.com/ghdl/setup-ghdl-ci) created, to allow easy installation of nightly GHDL assets in GitHub Actions workflows.
+- A [wiki](https://github.com/ghdl/ghdl/wiki) was created. The roadmap and ideas for documentation and internship programs were moved there.
+- Logo updated (org, ghdl/ghdl, ghdl/docker and ghdl/ghdl-cosim).
+- Assets not added to releases or pre-releases anymore. Users should use package managers or nightly assets (updated after each successful CI run of branch `master`): [nightly](https://github.com/ghdl/ghdl/releases/tag/nightly).
+- Main documentation site(s) moved to [ghdl.github.io/ghdl](https://ghdl.github.io/ghdl/) and [ghdl.github.io/ghdl-cosim](https://ghdl.github.io/ghdl-cosim/).
 
 **0.37** (2020-02-28)
 

doc/about.rst

@@ -12,64 +12,79 @@ About
 What is `VHDL`?
 ===============
 
-:wikipedia:`VHDL <VHDL>` is an acronym for Very High Speed Integrated Circuit (:wikipedia:`VHSIC <VHSIC>`) Hardware Description
-Language (:wikipedia:`HDL <HDL>`), which is a programming language used to describe a logic circuit by function, data flow
-behavior, or structure.
-
-Although VHDL was not designed for writing general purpose programs, VHDL *is* a programming language, and you can write any
-algorithm with it. If you are able to write programs, you will find in VHDL features similar to those found in procedural
-languages such as `C`, `Python`, or `Ada`. Indeed, VHDL derives most of its syntax and semantics from Ada. Knowing `Ada` is
-an advantage for learning VHDL (it is an advantage in general as well).
-
-However, VHDL was not designed as a general purpose language but as an `HDL`. As the name implies, VHDL aims at modeling or
-documenting electronics systems. Due to the nature of hardware components which are always running, VHDL is a highly
-concurrent language, built upon an event-based timing model.
-
-Like a program written in any other language, a VHDL program can be executed. Since VHDL is used to model designs, the term
-:dfn:`simulation` is often used instead of `execution`, with the same meaning. At the same time, like a design written in
-another `HDL`, a set of VHDL sources can be transformed with a :dfn:`synthesis tool` into a netlist, that is, a detailed
-gate-level implementation.
-
-The development of VHDL started in 1983 and the standard is named `IEEE <https://www.ieee.org/>`__ `1076`. Five revisions
-exist: `1987 <http://ieeexplore.ieee.org/document/26487/>`__, `1993 <http://ieeexplore.ieee.org/document/392561/>`__,
-`2002 <http://ieeexplore.ieee.org/document/1003477/>`__, `2008 <http://ieeexplore.ieee.org/document/4772740/>`__ and
-`2019 <https://ieeexplore.ieee.org/document/8938196>`__. The standardization is handled by the VHDL Analysis and
-Standardization Group (`VASG/P1076 <http://www.eda-twiki.org/vasg/>`__).
+:wikipedia:`VHDL <VHDL>` is an acronym for Very High Speed Integrated Circuit (:wikipedia:`VHSIC <VHSIC>`) Hardware
+Description Language (:wikipedia:`HDL <HDL>`), which is a programming language used to describe a logic circuit by
+function, data flow behavior, or structure.
+
+Although VHDL was not designed for writing general purpose programs, VHDL *is* a programming language, and you can write
+any algorithm with it.
+If you are able to write programs, you will find in VHDL features similar to those found in procedural languages such as
+`C`, `Python`, or `Ada`.
+Indeed, VHDL derives most of its syntax and semantics from Ada. Knowing `Ada` is an advantage for learning VHDL (it is
+an advantage in general as well).
+
+However, VHDL was not designed as a general purpose language but as an `HDL`.
+As the name implies, VHDL aims at modeling or documenting electronics systems.
+Due to the nature of hardware components which are always running, VHDL is a highly concurrent language, built upon an
+event-based timing model.
+
+Like a program written in any other language, a VHDL program can be executed.
+Since VHDL is used to model designs, the term :dfn:`simulation` is often used instead of `execution`, with the same
+meaning.
+At the same time, like a design written in another `HDL`, a set of VHDL sources can be transformed with a
+:dfn:`synthesis tool` into a netlist, that is, a detailed gate-level implementation.
+
+The development of VHDL started in 1983 and the standard is named `IEEE <https://www.ieee.org/>`__ `1076`.
+Five revisions exist:
+`1987 <http://ieeexplore.ieee.org/document/26487/>`__,
+`1993 <http://ieeexplore.ieee.org/document/392561/>`__,
+`2002 <http://ieeexplore.ieee.org/document/1003477/>`__,
+`2008 <http://ieeexplore.ieee.org/document/4772740/>`__ and
+`2019 <https://ieeexplore.ieee.org/document/8938196>`__.
+The standardization is handled by the VHDL Analysis and Standardization Group (`VASG/P1076 <http://www.eda-twiki.org/vasg/>`__).
 
 .. _INTRO:GHDL:
 
 What is GHDL?
 =============
 
-`GHDL` is a shorthand for `G Hardware Design Language` (currently, `G` has no meaning). It is a VHDL analyzer, compiler,
-simulator and (experimental) synthesizer that can process (nearly) any VHDL design.
+`GHDL` is a shorthand for `G Hardware Design Language` (currently, `G` has no meaning).
+It is a VHDL analyzer, compiler, simulator and (experimental) synthesizer that can process (nearly) any VHDL design.
 
 .. NOTE::
-  For almost 20 years, GHDL was *not* a synthesis tool: you could not create a netlist. Hence, most of the content in this
-  documentation corresponds to the usage of GHDL as a compiler/simulator. See :ref:`USING:Synthesis` for further details
-  regarding synthesis.
+  For almost 20 years, GHDL was *not* a synthesis tool: you could not create a netlist.
+  Hence, most of the content in this documentation corresponds to the usage of GHDL as a compiler/simulator.
+  See :ref:`USING:Synthesis` for further details regarding synthesis.
 
 Unlike some other simulators, GHDL is a compiler: it directly translates a VHDL file to machine code, without using an
-intermediary language such as `C` or `C++`. Therefore, the compiled code should be faster and the analysis time should be
-shorter than with a compiler using an intermediary language.
+intermediary language such as `C` or `C++`.
+Therefore, the compiled code should be faster and the analysis time should be shorter than with a compiler using an
+intermediary language.
 
 GHDL can use multiple back-ends, i.e. code generators, (`GCC <http://gcc.gnu.org/>`__, `LLVM <http://llvm.org/>`__ or
-:wikipedia:`x86 <X86-64>`/:wikipedia:`i386 <Intel_80386>` only, a built-in one named *mcode*) and runs on :wikipedia:`GNU/Linux <Linux_distribution>`,
-:wikipedia:`Windows <Microsoft_Windows>` |trade| and :wikipedia:`macOS <MacOS>` |trade|; on x86, x86_64, armv6/armv7/aarch32/aarch64,
-ppc64, etc.
-
-The current version of GHDL does not contain any built-in graphical viewer: you cannot see signal waves. You can still check
-the behavior of your design with a test bench. Moreover, `GHW <http://ghdl.readthedocs.io/en/latest/using/Simulation.html?highlight=GHW#cmdoption-wave>`__,
-:wikipedia:`VCD <Value_change_dump>` or `FST` files can be produced, which can be viewed with a :wikipedia:`waveform viewer <Waveform_viewer>`,
+:wikipedia:`x86 <X86-64>`/:wikipedia:`i386 <Intel_80386>` only, a built-in one named *mcode*) and runs on
+:wikipedia:`GNU/Linux <Linux_distribution>`, :wikipedia:`Windows <Microsoft_Windows>` |trade| and
+:wikipedia:`macOS <MacOS>` |trade|; on x86, x86_64, armv6/armv7/aarch32/aarch64, ppc64, etc.
+
+The current version of GHDL does not contain any built-in graphical viewer: you cannot see signal waves.
+You can still check the behavior of your design with a test bench.
+Moreover, :ref:`GHW`, :wikipedia:`VCD <Value_change_dump>` or `FST` files can be produced, which can be viewed with a
+:wikipedia:`waveform viewer <Waveform_viewer>`,
 such as `GtkWave <http://gtkwave.sourceforge.net/>`__.
 
-GHDL aims at implementing VHDL as defined by `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`__. It supports the
-`1987 <http://ieeexplore.ieee.org/document/26487/>`__, `1993 <http://ieeexplore.ieee.org/document/392561/>`__ and
-`2002 <http://ieeexplore.ieee.org/document/1003477/>`__ revisions and, partially, `2008 <http://ieeexplore.ieee.org/document/4772740/>`__.
+GHDL aims at implementing VHDL as defined by `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`__.
+It supports the
+`1987 <http://ieeexplore.ieee.org/document/26487/>`__,
+`1993 <http://ieeexplore.ieee.org/document/392561/>`__ and
+`2002 <http://ieeexplore.ieee.org/document/1003477/>`__ revisions and, partially,
+`2008 <http://ieeexplore.ieee.org/document/4772740/>`__.
 :wikipedia:`Property Specification Language (PSL) <Property_Specification_Language>` is also partially supported.
 
-Several third party projects are supported: `Yosys <https://github.com/YosysHQ/yosys>`__ (through the `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`__)
-`cocotb <https://github.com/potentialventures/cocotb>`__ (through the `VPI interface <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`__),
+Several third party projects are supported:
+`Yosys <https://github.com/YosysHQ/yosys>`__
+(through the `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`__)
+`cocotb <https://github.com/potentialventures/cocotb>`__
+(through the `VPI interface <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`__),
 `VUnit <https://vunit.github.io/>`__, `OSVVM <http://osvvm.org/>`__, ...
 
 .. _INTRO:WHO:

doc/development/CodingStyle.rst

@@ -227,7 +227,7 @@ Documentation configuration
 * Create "parts" (LaTeX terminology / chapter headlines) in navigation bar. [:ghdlsharp:`200`]
 
 * Intersphinx files [:ghdlsharp:`200`]
-	* To decompress the inventory file: `curl -s http://ghdl.readthedocs.io/en/latest/objects.inv | tail -n+5 | openssl zlib -d`. From `how-to-uncompress-zlib-data-in-unix <http://unix.stackexchange.com/questions/22834/how-to-uncompress-zlib-data-in-unix>`_.
+	* To decompress the inventory file: ``curl -s http://ghdl.github.io/ghdl/objects.inv | tail -n+5 | openssl zlib -d``. From `how-to-uncompress-zlib-data-in-unix <http://unix.stackexchange.com/questions/22834/how-to-uncompress-zlib-data-in-unix>`_.
 	* External ref and link to section::
 
 		:ref:`GHDL Roadmap <ghdl:CHANGE:Roadmap>`

doc/development/building/GCC.rst

@@ -9,7 +9,7 @@ GCC backend
 
 * GCC (Gnu Compiler Collection)
 * GNAT (Ada compiler for GCC)
-* GCC source files. Download and untar the sources of version 4.9.x, 5.x, 6.x, 7.x, 8.x, 9.x or 10.x (`GCC mirror sites <https://gcc.gnu.org/mirrors.html`__).
+* GCC source files. Download and untar the sources of version 4.9.x, 5.x, 6.x, 7.x, 8.x, 9.x, 10.x or 11.x (`GCC mirror sites <https://gcc.gnu.org/mirrors.html>`__).
 
 .. HINT :: There are some dependencies for building GCC (``gmp``, ``mpfr`` and ``mpc``). If you have not installed them on your system, you can either build them manually or use the ``download_prerequisites`` script provided in the GCC source tree (recommended): ``cd /path/to/gcc/source/dir && ./contrib/download_prerequisites``.
 

doc/index.rst

@@ -29,6 +29,9 @@ GHDL
    News
    ****
 
+   02.02.2021 - `GHDL v1.0 was released <https://github.com/ghdl/ghdl/milestone/9?closed=1>`__
+   ============================================================================================
+
    31.01.2021 - GHDL v1.0.0rc1 was tagged
    ======================================
 
@@ -102,6 +105,8 @@ GHDL
 
 .. only:: latex
 
+   .. rubric:: 02.02.2021 - GHDL v1.0 was released.
+
    .. rubric:: 31.01.2021 - GHDL v1.0.0rc1 was tagged.
 
    .. rubric:: 21.05.2020 - Nightly build assets available.