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added annotation files for every unit test

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gokhankici committed Jun 12, 2019
1 parent 4a12c01 commit 0e7c805c33d3f35dd7956b09f56faa483f2cfbb8
Showing with 1,090 additions and 27 deletions.
  1. +68 −0 benchmarks/472-mips-pipelined/annot-472-mips-fragment-2.json
  2. +68 −0 benchmarks/472-mips-pipelined/annot-472-mips-fragment-3.json
  3. +76 −0 benchmarks/472-mips-pipelined/annot-472-mips-fragment-4.json
  4. +68 −0 benchmarks/472-mips-pipelined/annot-472-mips-fragment.json
  5. +19 −0 benchmarks/472-mips-pipelined/annot-alu.json
  6. +23 −0 benchmarks/472-mips-pipelined/annot-alu_ctl.json
  7. +30 −0 benchmarks/472-mips-pipelined/annot-control_pipeline.json
  8. +22 −0 benchmarks/472-mips-pipelined/annot-mux3.json
  9. +22 −0 benchmarks/472-mips-pipelined/annot-reg32.json
  10. +36 −0 benchmarks/472-mips-pipelined/annot-reg_file.json
  11. +22 −0 benchmarks/472-mips-pipelined/annot-rom32.json
  12. +0 −9 benchmarks/472-mips-pipelined/reg_file.v
  13. +28 −0 examples/verilog/annot-stall.json
  14. +41 −7 scripts/parse_old_annotations.py
  15. +1 −0 src/Iodine/Language/AnnotParser.hs
  16. +13 −11 test/Test.hs
  17. +27 −0 test/verilog/neg/annot-neg-merge-01.json
  18. +16 −0 test/verilog/neg/annot-neg-test-1.json
  19. +35 −0 test/verilog/neg/annot-neg-test-11.json
  20. +35 −0 test/verilog/neg/annot-neg-test-2.json
  21. +32 −0 test/verilog/neg/annot-neg-test-5.json
  22. +22 −0 test/verilog/neg/annot-secverilog-neg-01.json
  23. +33 −0 test/verilog/neg/annot-secverilog-neg-02.json
  24. +34 −0 test/verilog/neg/annot-tp.json
  25. +17 −0 test/verilog/pos/annot-merge-02.json
  26. +33 −0 test/verilog/pos/annot-merge03.json
  27. +34 −0 test/verilog/pos/annot-merge04.json
  28. +24 −0 test/verilog/pos/annot-secverilog-01.json
  29. +16 −0 test/verilog/pos/annot-tr-test-1.json
  30. +33 −0 test/verilog/pos/annot-tr-test-10.json
  31. +36 −0 test/verilog/pos/annot-tr-test-11.json
  32. +22 −0 test/verilog/pos/annot-tr-test-2.json
  33. +22 −0 test/verilog/pos/annot-tr-test-3.json
  34. +22 −0 test/verilog/pos/annot-tr-test-4.json
  35. +22 −0 test/verilog/pos/annot-tr-test-5.json
  36. +22 −0 test/verilog/pos/annot-tr-test-6.json
  37. +16 −0 test/verilog/pos/annot-tr-test-9.json
@@ -0,0 +1,68 @@
{
"annotations": [
{
"type": "source",
"variables": [
"IF_instr"
]
},
{
"type": "sink",
"variables": [
"ID_instr"
]
},
{
"type": "always_eq",
"variables": [
"IF_instr"
]
},
{
"type": "initial_eq",
"variables": [
"EX_ALUOp",
"EX_MemRead",
"EX_extend",
"EX_rt",
"ID_instr",
"IF_instr",
"MEM_ALUOut",
"Stall",
"WB_ALUOut",
"a",
"b"
]
},
{
"type": "initial_eq",
"variables": [
"ALUOp",
"ALUSrc",
"Branch",
"Jump",
"MemRead",
"MemWrite",
"MemtoReg",
"RegDst",
"RegWrite"
],
"module": "control_pipeline"
},
{
"type": "initial_eq",
"variables": [
"ALUOperation"
],
"module": "alu_ctl_stub"
},
{
"type": "initial_eq",
"variables": [
"result",
"zero"
],
"module": "alu_stub"
}
]
}
@@ -0,0 +1,68 @@
{
"annotations": [
{
"type": "source",
"variables": [
"IF_instr"
]
},
{
"type": "sink",
"variables": [
"ID_instr"
]
},
{
"type": "always_eq",
"variables": [
"IF_instr"
]
},
{
"type": "initial_eq",
"variables": [
"EX_ALUOp",
"EX_MemRead",
"EX_extend",
"EX_rt",
"ID_instr",
"IF_instr",
"MEM_ALUOut",
"Stall",
"WB_ALUOut",
"a",
"b"
]
},
{
"type": "initial_eq",
"variables": [
"ALUOp",
"ALUSrc",
"Branch",
"Jump",
"MemRead",
"MemWrite",
"MemtoReg",
"RegDst",
"RegWrite"
],
"module": "control_pipeline"
},
{
"type": "initial_eq",
"variables": [
"ALUOperation"
],
"module": "alu_ctl"
},
{
"type": "initial_eq",
"variables": [
"result",
"zero"
],
"module": "alu"
}
]
}
@@ -0,0 +1,76 @@
{
"annotations": [
{
"type": "source",
"variables": [
"ID_instr"
]
},
{
"type": "sink",
"variables": [
"EX_rt"
]
},
{
"type": "always_eq",
"variables": [
"reset"
]
},
{
"type": "initial_eq",
"variables": [
"EX_ALUOp",
"EX_ALUSrc",
"EX_Branch",
"EX_MemRead",
"EX_MemWrite",
"EX_MemtoReg",
"EX_RegDst",
"EX_RegWrite",
"EX_extend",
"EX_pc4",
"EX_rd",
"EX_rd1",
"EX_rd2",
"EX_rs",
"EX_rt",
"ForwardA",
"ForwardB",
"ID_instr",
"MEM_ALUOut",
"MEM_Branch",
"MEM_MemRead",
"MEM_MemWrite",
"MEM_MemtoReg",
"MEM_RegRd",
"MEM_RegWrite",
"MEM_Zero",
"MEM_btgt",
"MEM_rd2",
"Stall",
"WB_ALUOut",
"WB_MemtoReg",
"WB_RegRd",
"WB_RegWrite",
"WB_memout"
]
},
{
"type": "initial_eq",
"variables": [
"ALUOp",
"ALUSrc",
"Branch",
"Jump",
"MemRead",
"MemWrite",
"MemtoReg",
"RegDst",
"RegWrite"
],
"module": "control_pipeline"
}
]
}
@@ -0,0 +1,68 @@
{
"annotations": [
{
"type": "source",
"variables": [
"IF_instr"
]
},
{
"type": "sink",
"variables": [
"ID_instr"
]
},
{
"type": "always_eq",
"variables": [
"IF_instr"
]
},
{
"type": "initial_eq",
"variables": [
"EX_ALUOp",
"EX_MemRead",
"EX_extend",
"EX_rt",
"ID_instr",
"IF_instr",
"MEM_ALUOut",
"Stall",
"WB_ALUOut",
"a",
"b"
]
},
{
"type": "initial_eq",
"variables": [
"ALUOp",
"ALUSrc",
"Branch",
"Jump",
"MemRead",
"MemWrite",
"MemtoReg",
"RegDst",
"RegWrite"
],
"module": "control_pipeline_stub"
},
{
"type": "initial_eq",
"variables": [
"ALUOperation"
],
"module": "alu_ctl_stub"
},
{
"type": "initial_eq",
"variables": [
"result",
"zero"
],
"module": "alu_stub"
}
]
}
@@ -0,0 +1,19 @@
{
"annotations": [
{
"type": "source",
"variables": [
"a",
"b",
"ctl"
]
},
{
"type": "sink",
"variables": [
"result",
"zero"
]
}
]
}
@@ -0,0 +1,23 @@
{
"annotations": [
{
"type": "source",
"variables": [
"ALUOperation"
]
},
{
"type": "sink",
"variables": [
"ALUOperation"
]
},
{
"type": "always_eq",
"variables": [
"ALUOp",
"Funct"
]
}
]
}
@@ -0,0 +1,30 @@
{
"annotations": [
{
"type": "source",
"variables": [
"ALUSrc",
"Branch",
"Jump",
"MemRead",
"MemWrite",
"MemtoReg",
"RegDst",
"RegWrite"
]
},
{
"type": "sink",
"variables": [
"ALUSrc",
"Branch",
"Jump",
"MemRead",
"MemWrite",
"MemtoReg",
"RegDst",
"RegWrite"
]
}
]
}
@@ -0,0 +1,22 @@
{
"annotations": [
{
"type": "source",
"variables": [
"y"
]
},
{
"type": "sink",
"variables": [
"y"
]
},
{
"type": "always_eq",
"variables": [
"sel"
]
}
]
}

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