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added annotation files for every unit test
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68 changes: 68 additions & 0 deletions
68
benchmarks/472-mips-pipelined/annot-472-mips-fragment-2.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,68 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "IF_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "ID_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "always_eq", | ||
| "variables": [ | ||
| "IF_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "EX_ALUOp", | ||
| "EX_MemRead", | ||
| "EX_extend", | ||
| "EX_rt", | ||
| "ID_instr", | ||
| "IF_instr", | ||
| "MEM_ALUOut", | ||
| "Stall", | ||
| "WB_ALUOut", | ||
| "a", | ||
| "b" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOp", | ||
| "ALUSrc", | ||
| "Branch", | ||
| "Jump", | ||
| "MemRead", | ||
| "MemWrite", | ||
| "MemtoReg", | ||
| "RegDst", | ||
| "RegWrite" | ||
| ], | ||
| "module": "control_pipeline" | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOperation" | ||
| ], | ||
| "module": "alu_ctl_stub" | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "result", | ||
| "zero" | ||
| ], | ||
| "module": "alu_stub" | ||
| } | ||
| ] | ||
| } |
68 changes: 68 additions & 0 deletions
68
benchmarks/472-mips-pipelined/annot-472-mips-fragment-3.json
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|---|---|---|
| @@ -0,0 +1,68 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "IF_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "ID_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "always_eq", | ||
| "variables": [ | ||
| "IF_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "EX_ALUOp", | ||
| "EX_MemRead", | ||
| "EX_extend", | ||
| "EX_rt", | ||
| "ID_instr", | ||
| "IF_instr", | ||
| "MEM_ALUOut", | ||
| "Stall", | ||
| "WB_ALUOut", | ||
| "a", | ||
| "b" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOp", | ||
| "ALUSrc", | ||
| "Branch", | ||
| "Jump", | ||
| "MemRead", | ||
| "MemWrite", | ||
| "MemtoReg", | ||
| "RegDst", | ||
| "RegWrite" | ||
| ], | ||
| "module": "control_pipeline" | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOperation" | ||
| ], | ||
| "module": "alu_ctl" | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "result", | ||
| "zero" | ||
| ], | ||
| "module": "alu" | ||
| } | ||
| ] | ||
| } |
76 changes: 76 additions & 0 deletions
76
benchmarks/472-mips-pipelined/annot-472-mips-fragment-4.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,76 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "ID_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "EX_rt" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "always_eq", | ||
| "variables": [ | ||
| "reset" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "EX_ALUOp", | ||
| "EX_ALUSrc", | ||
| "EX_Branch", | ||
| "EX_MemRead", | ||
| "EX_MemWrite", | ||
| "EX_MemtoReg", | ||
| "EX_RegDst", | ||
| "EX_RegWrite", | ||
| "EX_extend", | ||
| "EX_pc4", | ||
| "EX_rd", | ||
| "EX_rd1", | ||
| "EX_rd2", | ||
| "EX_rs", | ||
| "EX_rt", | ||
| "ForwardA", | ||
| "ForwardB", | ||
| "ID_instr", | ||
| "MEM_ALUOut", | ||
| "MEM_Branch", | ||
| "MEM_MemRead", | ||
| "MEM_MemWrite", | ||
| "MEM_MemtoReg", | ||
| "MEM_RegRd", | ||
| "MEM_RegWrite", | ||
| "MEM_Zero", | ||
| "MEM_btgt", | ||
| "MEM_rd2", | ||
| "Stall", | ||
| "WB_ALUOut", | ||
| "WB_MemtoReg", | ||
| "WB_RegRd", | ||
| "WB_RegWrite", | ||
| "WB_memout" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOp", | ||
| "ALUSrc", | ||
| "Branch", | ||
| "Jump", | ||
| "MemRead", | ||
| "MemWrite", | ||
| "MemtoReg", | ||
| "RegDst", | ||
| "RegWrite" | ||
| ], | ||
| "module": "control_pipeline" | ||
| } | ||
| ] | ||
| } |
68 changes: 68 additions & 0 deletions
68
benchmarks/472-mips-pipelined/annot-472-mips-fragment.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,68 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "IF_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "ID_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "always_eq", | ||
| "variables": [ | ||
| "IF_instr" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "EX_ALUOp", | ||
| "EX_MemRead", | ||
| "EX_extend", | ||
| "EX_rt", | ||
| "ID_instr", | ||
| "IF_instr", | ||
| "MEM_ALUOut", | ||
| "Stall", | ||
| "WB_ALUOut", | ||
| "a", | ||
| "b" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOp", | ||
| "ALUSrc", | ||
| "Branch", | ||
| "Jump", | ||
| "MemRead", | ||
| "MemWrite", | ||
| "MemtoReg", | ||
| "RegDst", | ||
| "RegWrite" | ||
| ], | ||
| "module": "control_pipeline_stub" | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "ALUOperation" | ||
| ], | ||
| "module": "alu_ctl_stub" | ||
| }, | ||
| { | ||
| "type": "initial_eq", | ||
| "variables": [ | ||
| "result", | ||
| "zero" | ||
| ], | ||
| "module": "alu_stub" | ||
| } | ||
| ] | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "a", | ||
| "b", | ||
| "ctl" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "result", | ||
| "zero" | ||
| ] | ||
| } | ||
| ] | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "ALUOperation" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "ALUOperation" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "always_eq", | ||
| "variables": [ | ||
| "ALUOp", | ||
| "Funct" | ||
| ] | ||
| } | ||
| ] | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,30 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "ALUSrc", | ||
| "Branch", | ||
| "Jump", | ||
| "MemRead", | ||
| "MemWrite", | ||
| "MemtoReg", | ||
| "RegDst", | ||
| "RegWrite" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "ALUSrc", | ||
| "Branch", | ||
| "Jump", | ||
| "MemRead", | ||
| "MemWrite", | ||
| "MemtoReg", | ||
| "RegDst", | ||
| "RegWrite" | ||
| ] | ||
| } | ||
| ] | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,22 @@ | ||
| { | ||
| "annotations": [ | ||
| { | ||
| "type": "source", | ||
| "variables": [ | ||
| "y" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "sink", | ||
| "variables": [ | ||
| "y" | ||
| ] | ||
| }, | ||
| { | ||
| "type": "always_eq", | ||
| "variables": [ | ||
| "sel" | ||
| ] | ||
| } | ||
| ] | ||
| } |
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