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runtime/internal/atomic: Remove unnecessary checks for GOARCH_ppc64
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Starting in go1.9, the minimum processor requirement for ppc64 is POWER8. This
means the checks for GOARCH_ppc64 in asm_ppc64x.s can be removed, since we can
assume LBAR and STBCCC instructions (both from ISA 2.06) will always be
available.

Updates #19074

Change-Id: Ib4418169cd9fc6f871a5ab126b28ee58a2f349e2
Reviewed-on: https://go-review.googlesource.com/38406
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
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ceseo authored and laboger committed Mar 22, 2017
1 parent 22ea7fc commit 189053a
Showing 1 changed file with 0 additions and 43 deletions.
43 changes: 0 additions & 43 deletions src/runtime/internal/atomic/asm_ppc64x.s
Expand Up @@ -165,67 +165,24 @@ TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-16
TEXT runtime∕internal∕atomic·Or8(SB), NOSPLIT, $0-9
MOVD ptr+0(FP), R3
MOVBZ val+8(FP), R4
#ifdef GOARCH_ppc64
// Align ptr down to 4 bytes so we can use 32-bit load/store.
// R5 = (R3 << 0) & ~3
RLDCR $0, R3, $~3, R5
// Compute val shift.
// Big endian. ptr = ptr ^ 3
XOR $3, R3
// R6 = ((ptr & 3) * 8) = (ptr << 3) & (3*8)
RLDC $3, R3, $(3*8), R6
// Shift val for aligned ptr. R4 = val << R6
SLD R6, R4, R4
SYNC

again:
LWAR (R5), R6
OR R4, R6
STWCCC R6, (R5)
BNE again
#else
SYNC
again:
LBAR (R3), R6
OR R4, R6
STBCCC R6, (R3)
BNE again
#endif
ISYNC
RET

// void runtime∕internal∕atomic·And8(byte volatile*, byte);
TEXT runtime∕internal∕atomic·And8(SB), NOSPLIT, $0-9
MOVD ptr+0(FP), R3
MOVBZ val+8(FP), R4
#ifdef GOARCH_ppc64
// Align ptr down to 4 bytes so we can use 32-bit load/store.
// R5 = (R3 << 0) & ~3
RLDCR $0, R3, $~3, R5
// Compute val shift.
// Big endian. ptr = ptr ^ 3
XOR $3, R3
// R6 = ((ptr & 3) * 8) = (ptr << 3) & (3*8)
RLDC $3, R3, $(3*8), R6
// Shift val for aligned ptr. R4 = val << R6 | ^(0xFF << R6)
MOVD $0xFF, R7
SLD R6, R4
SLD R6, R7
XOR $-1, R7
OR R7, R4
SYNC
again:
LWAR (R5), R6
AND R4, R6
STWCCC R6, (R5)
BNE again
#else
SYNC
again:
LBAR (R3),R6
AND R4,R6
STBCCC R6,(R3)
BNE again
#endif
ISYNC
RET

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