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Break out verilog module, mostly
#15
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… SUBCKT case-sensitivity. Fail when encountering Verilog ast.Assign
growly
reviewed
May 16, 2022
| @@ -447,8 +53,11 @@ def DefineOptions(optparser): | |||
| optparser.add_option('--verilog_include', dest='verilog_includes', default=[], action='append', help='verilog include paths') | |||
| optparser.add_option('--verilog_defines', dest='verilog_defines', default=[], action='append', help='verilog macro definitions') | |||
| optparser.add_option('--spef', dest='spef_files', default=[], action='append', help='spef files') | |||
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| # FIXME: what is the difference between these two "spice" options? | |||
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--spice files are read for their contents (i.e. a circuit.Module is loaded from their netlists)
--spice_headers are read for their port orders and kept as ExternalModules
growly
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May 16, 2022
circuit.py
Outdated
| @@ -563,9 +561,16 @@ def __init__(self, ast_node=None): | |||
| self.time_unit_prefix = None | |||
| # How many 10^x of a Henry. (None => x = 0) | |||
| self.inductance_unit_prefix = None | |||
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| @classmethod | |||
| def from_verilog(cls, ast_node: "verilog.ast.Node") -> "Module": | |||
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keep consistent with style in rest of project: FromVerilog
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FWIW, noticed this in the style guide: Code that is to be released as open source should follow the public style guide on GitHub instead. And that (https://google.github.io/styleguide/pyguide#3164-guidelines-derived-from-guidos-recommendations) says: So, I suppose this is really a much larger AI for the maintainer! |
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👀 oh no they changed everything |
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ast.Assign