Add BlackIce-II support

.gitignore

@@ -8,6 +8,7 @@
 *.rpt
 *.stat
 /pll.sv
+/defines.sv
 /progmem
 !.git*
 !.mailmap

Makefile

@@ -30,7 +30,7 @@ include boards/$(BOARD).mk
 all: $(BIN)
 
 clean:
-	$(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) $(TIME_RPT) $(STAT) progmem_syn.hex progmem.hex progmem.o start.o progmem
+	$(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) $(TIME_RPT) $(STAT) progmem_syn.hex progmem.hex progmem.o start.o progmem defines.sv
 
 progmem.hex: progmem
 	$(OBJCOPY) -O binary $< /dev/stdout \
@@ -45,12 +45,15 @@ progmem_syn.hex:
 $(PLL):
 	icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
 
-$(BLIF): $(TCL) $(SRC) progmem_syn.hex
+$(BLIF): $(TCL) $(SRC) progmem_syn.hex defines.sv
 	IC=$(SPEED)$(DEVICE) yosys $(QUIET) $<
 
-syntax: $(SRC) progmem_syn.hex
+syntax: $(SRC) progmem_syn.hex defines.sv
 	iverilog -Wall -t null -g2012 $(YS_ICE40) $(SV)
 
+defines.sv: boards/$(BOARD)-defines.sv
+	cp boards/$(BOARD)-defines.sv defines.sv
+
 $(ASC_SYN): $(BLIF) $(PCF)
 	arachne-pnr $(QUIET) -d $(DEVICE) -P $(PACKAGE) -o $@ -p $(PCF) $<
 
@@ -74,3 +77,8 @@ stat: $(STAT)
 
 flash: $(BIN) $(TIME_RPT)
 	iceprog -S $<
+
+# Flash to BlackIce-II board
+dfu-flash: $(BIN) $(TIME_RPT)
+	dfu-util -d 0483:df11 --alt 0 --dfuse-address 0x0801F000 -D $(BIN)
+

boards/blackice-ii-defines.sv

@@ -0,0 +1 @@
+// Defines for BlackIce-II

boards/blackice-ii.mk

@@ -0,0 +1,4 @@
+SPEED    = hx
+DEVICE   = 8k
+PACKAGE  = tq144:4k
+FREQ_OSC = 100

boards/blackice-ii.pcf

@@ -0,0 +1,15 @@
+set_io clk       129
+
+set_io leds[0]   70
+set_io leds[1]   68
+set_io leds[2]   67
+set_io leds[3]   71
+
+# Connected to regular GPIOs, not LEDs
+set_io leds[4]   20
+set_io leds[5]   19
+set_io leds[6]   16
+set_io leds[7]   15
+
+set_io uart_rx   88
+set_io uart_tx   85

boards/ice40hx8k-b-evn-defines.sv

@@ -0,0 +1,2 @@
+// Defines for iCE40-HX8K breakout board
+`define FLASH

boards/upduino-defines.sv

@@ -0,0 +1,2 @@
+// Defines for Upduino
+`define FLASH

top.sv

@@ -1,3 +1,4 @@
+`include "defines.sv"
 `include "bus_arbiter.sv"
 `include "pll.sv"
 `include "ram.sv"
@@ -11,11 +12,13 @@ module top (
     input clk,
 `endif
 
+`ifdef FLASH
     /* serial flash */
     output logic flash_clk,
     output logic flash_csn,
     inout flash_io0,
     inout flash_io1,
+`endif
 
     /* LEDs */
     output logic [7:0] leds,
@@ -24,13 +27,16 @@ module top (
     input uart_rx,
     output logic uart_tx
 );
+
+`ifdef FLASH
     logic flash_io0_en;
     logic flash_io0_in;
     logic flash_io0_out;
 
     logic flash_io1_en;
     logic flash_io1_in;
     logic flash_io1_out;
+`endif
 
 `ifdef up5k
     wire clk;
@@ -41,6 +47,7 @@ module top (
     );
 `endif
 
+`ifdef FLASH
     SB_IO #(
         .PIN_TYPE(6'b1010_01)
     ) flash_io [1:0] (
@@ -49,6 +56,7 @@ module top (
         .D_IN_0({flash_io1_in, flash_io0_in}),
         .D_OUT_0({flash_io1_out, flash_io0_out})
     );
+`endif
 
     logic pll_clk;
     logic pll_locked_async;