Merge pull request #1661 from nicolasnoble/more-cpu-tests

More CPU tests
grumpycoders · Jun 11, 2024 · 4be370f · 4be370f
2 parents ac177b3 + 7efd6ba
commit 4be370f
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Showing 4 changed files with 65 additions and 1 deletion.
diff --git a/src/mips/tests/cop0/cester-cop0.c b/src/mips/tests/cop0/cester-cop0.c
@@ -71,8 +71,11 @@ CESTER_BODY(
     uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial);
     uint32_t cpu_LWR_LWL_nodelay(uint32_t buff[], uint32_t initial);
     uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial);
+    uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial);
+    uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial);
     uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override);
     uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override);
+    uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override);
     uint32_t linkandload();
     uint32_t lwandlink();
     uint32_t nolink();

diff --git a/src/mips/tests/cpu/cpu.c b/src/mips/tests/cpu/cpu.c
@@ -83,6 +83,18 @@ CESTER_TEST(cpu_LWR_LWL_delayed, cpu_tests,
     cester_assert_uint_eq(0x88112233, out);
 )
 
+CESTER_TEST(cpu_LWR_LWL_load_different, cpu_tests,
+    uint32_t buff[3] = {0x11223344, 0x55667788, 0xaabbccdd};
+    uint32_t out = cpu_LWR_LWL_load_different(buff, 0xeeffeffe);
+    cester_assert_uint_eq(0x88556677, out);
+)
+
+CESTER_TEST(cpu_LW_LWR, cpu_tests,
+    uint32_t buff[3] = {0x11223344, 0x55667788, 0xaabbccdd};
+    uint32_t out = cpu_LW_LWR(buff, 0xeeffeffe);
+    cester_assert_uint_eq(0xaa112233, out);
+)
+
 CESTER_TEST(cpu_delayed_load, cpu_tests,
     uint32_t buff[1] = {1};
     // As lw has a delayed load, the old value of the loaded
@@ -100,10 +112,19 @@ CESTER_TEST(cpu_delayed_load_cancelled, cpu_tests,
     // move into the same register, the delayed load is
     // cancelled, and the register will contain the new
     // value
-    uint32_t out = cpu_delayed_load(buff, 0);
+    uint32_t out = cpu_delayed_load_cancelled(buff, 0);
     cester_assert_uint_eq(0, out);
 )
 
+CESTER_MAYBE_TEST(cpu_delayed_load_load, cpu_tests,
+    uint32_t buff[2] = {1, 2};
+    // The above becomes complicated once you have two
+    // lw instructions in a row loading the same register
+    uint64_t out = cpu_delayed_load_load(buff, 4);
+    out = ((out >> 16) | out) & 0xffffffff;
+    cester_assert_uint_eq(0x00020004, out);
+)
+
 CESTER_MAYBE_TEST(cpu_BRANCH_BRANCH_slot, cpu_tests,
     // running a branch in a branch delay slot is technically
     // not allowed, but some games still do this, and the

diff --git a/src/mips/tests/cpu/loads.s b/src/mips/tests/cpu/loads.s
@@ -32,6 +32,7 @@ SOFTWARE.
     .type cpu_delayed_load, @function
 
 /* This can happen. */
+/* uint32_t cpu_delayed_load(uint32_t buff[], uint32_t override); */
 cpu_delayed_load:
     lw    $a1, 0($a0)
     move  $v0, $a1
@@ -43,8 +44,23 @@ cpu_delayed_load:
     .type cpu_delayed_load_cancelled, @function
 
 /* This happens even more frequently. */
+/* uint32_t cpu_delayed_load_cancelled(uint32_t buff[], uint32_t override); */
 cpu_delayed_load_cancelled:
     lw    $v0, 0($a0)
     move  $v0, $a1
     jr    $ra
     nop
+
+    .align 2
+    .global cpu_delayed_load_load
+    .type cpu_delayed_load_load, @function
+
+/* This is extremely infrequent */
+/* uint64_t cpu_delayed_load_load(uint32_t buff[], uint32_t override); */
+cpu_delayed_load_load:
+    lw    $a1, 0($a0)
+    lw    $a1, 4($a0)
+    move  $v0, $a1
+    move  $v1, $a1
+    jr    $ra
+    nop
diff --git a/src/mips/tests/cpu/lwlr.s b/src/mips/tests/cpu/lwlr.s
@@ -32,6 +32,7 @@ SOFTWARE.
     .type cpu_LWR_LWL_half, @function
 
 /* While this usage is rare, it is technically valid and allowed. */
+/* uint32_t cpu_LWR_LWL_half(uint32_t buff[], uint32_t initial); */
 cpu_LWR_LWL_half:
     lwl   $a1, 4($a0)
     jr    $ra
@@ -43,6 +44,7 @@ cpu_LWR_LWL_half:
 
 /* This is technically invalid, and undefined behaviour. The result will be
    deterministic however on the r3000a PSX CPU. */
+/* uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial); */
 cpu_LWR_LWL_nodelay:
     lwl   $a1, 4($a0)
     lwr   $a1, 1($a0)
@@ -55,8 +57,30 @@ cpu_LWR_LWL_nodelay:
     .type cpu_LWR_LWL_delayed, @function
 
 /* This is the proper usage of lwl / lwr. */
+/* uint32_t cpu_LWR_LWL_delayed(uint32_t buff[], uint32_t initial); */
 cpu_LWR_LWL_delayed:
     lwl   $a1, 4($a0)
     lwr   $a1, 1($a0)
     j     $ra
     move  $v0, $a1
+
+    .align 2
+    .global cpu_LWR_LWL_load_different
+    .type cpu_LWR_LWL_load_different, @function
+
+/* uint32_t cpu_LWR_LWL_load_different(uint32_t buff[], uint32_t initial); */
+cpu_LWR_LWL_load_different:
+    lwl   $a1, 4($a0)
+    lwr   $a1, 5($a0)
+    j     $ra
+    move  $v0, $a1
+
+    .align 2
+    .global cpu_LW_LWR
+    .type cpu_LW_LWL, @function
+/* uint32_t cpu_LW_LWR(uint32_t buff[], uint32_t initial); */
+cpu_LW_LWR:
+    lw    $a1, 8($a0)
+    lwr   $a1, 1($a0)
+    j     $ra
+    move  $v0, $a1