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T80: Revert for demo 70908
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@gyurco
gyurco committed May 20, 2020
1 parent 75d8561 commit 8bb2d07
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Showing 2 changed files with 147 additions and 107 deletions.
220 changes: 136 additions & 84 deletions t80/T80.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,8 @@ entity T80 is
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
Flag_S : integer := 7;
USE_FALLING_EDGE_INTN : boolean:=false
);
port(
RESET_n : in std_logic;
Expand Down Expand Up @@ -174,6 +175,7 @@ architecture rtl of T80 is
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);

signal DI_Reg : std_logic_vector(7 downto 0);
Expand Down Expand Up @@ -1052,11 +1054,40 @@ begin

-------------------------------------------------------------------------
--
-- Main state machine
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif rising_edge(CLK_n) then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;

-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable wasINT_s_0:boolean:=false;
variable just_rising_INT_s:boolean:=false;
variable thats_rock:boolean:=false;
begin
if RESET_n = '0' then
MCycle <= "001";
Expand All @@ -1072,104 +1103,125 @@ begin
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
BusReq_s <= '0';
NMI_s <= '0';
elsif rising_edge(CLK_n) then

if DIRSet = '1' then
IntE_FF2 <= DIR(211);
IntE_FF1 <= DIR(210);

if INT_s = '1' and wasINT_s_0 then
just_rising_INT_s:=true;
end if;
if INT_s = '0' then
wasINT_s_0:=true;
else
wasINT_s_0:=false;
end if;
if CEN = '1' then
if T_Res = '1' then
Auto_Wait_t1 <= '0';
else
if NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
Auto_Wait_t1 <= Auto_Wait or IORQ_i;
end if;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
OldNMI_n := NMI_n;

if CEN = '1' then
BusReq_s <= not BUSRQ_n;
Auto_Wait_t2 <= Auto_Wait_t1;
if T_Res = '1' then
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
else
Auto_Wait_t1 <= Auto_Wait or IORQ_i;
end if;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
if BusReq_s = '1' then
BusAck <= '1';
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or (MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or No_BTR = '1' or (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMI_s <= '0';
NMICycle <= '1';
IntE_FF1 <= '0';
elsif IntE_FF1 = '1' and INT_n='0' and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
if not(thats_rock) then
IntCycle <= '0';
end if;
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and ((USE_FALLING_EDGE_INTN and just_rising_INT_s) or (not(USE_FALLING_EDGE_INTN) and INT_s='1') )) and Prefix = "00" and SetEI = '0' then
if USE_FALLING_EDGE_INTN then
thats_rock:=true;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
IntCycle <= '1';

end if;
else
if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
TState <= TState + 1;
elsif MCycle="010" then
if thats_rock then
thats_rock:=false;
just_rising_INT_s:=false;
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
if TState = 0 then
M1_n <= '0';
else
if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;

process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;

Auto_Wait <= '1' when IntCycle = '1' and MCycle = "001" else '0';
--Auto_Wait <= '1' when IntCycle = '1' and MCycle = "001" else '0';
end;
34 changes: 11 additions & 23 deletions t80/T80pa.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,11 +47,6 @@
--
-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
--
-- v2.2: Interrupt acknowledge cycle has been corrected
-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
--
-- v2.3: Output last used Address during non-bus MCycle seems more correct.
--

library IEEE;
use IEEE.std_logic_1164.all;
Expand Down Expand Up @@ -91,21 +86,20 @@ end T80pa;
architecture rtl of T80pa is

signal IntCycle_n : std_logic;
signal IntCycleD_n : std_logic_vector(1 downto 0);
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal BUSAK : std_logic;
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal CEN_pol : std_logic;
signal A_int : std_logic_vector(15 downto 0);
signal A_last : std_logic_vector(15 downto 0);

begin

A <= A_int when NoRead = '0' or Write = '1' else A_last;
A <= A_int when NoRead = '0' or Write = '1' else (others => '0');

BUSAK_n <= BUSAK;

Expand All @@ -122,7 +116,7 @@ begin
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => '1',
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
Expand Down Expand Up @@ -151,12 +145,12 @@ begin
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
Wait_s <= '1';
CEN_pol <= '0';
elsif CEN_p = '1' and CEN_pol = '0' then
CEN_pol <= '1';
if MCycle = "001" then
if TState = "010" then
IORQ_n <= '1';
MREQ_n <= '1';
RD_n <= '1';
end if;
Expand All @@ -168,25 +162,20 @@ begin
end if;
end if;
elsif CEN_n = '1' and CEN_pol = '1' then
if TState = "010" then
CEN_pol <= not WAIT_n;
else
CEN_pol <= '0';
end if;
CEN_pol <= '0';
Wait_s <= WAIT_n;
if TState = "011" and BUSAK = '1' then
DI_Reg <= DI;
end if;
if MCycle = "001" then
if TState = "001" then
IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycleD_n(1);
A_last <= A_int;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
IntCycleD_n <= "11";
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '0';
end if;
if TState = "100" then
Expand All @@ -197,11 +186,10 @@ begin
if TState = "001" then
RD_n <= Write;
MREQ_n <= '0';
A_last <= A_int;
end if;
end if;
if TState = "010" then
WR_n <= not Write;
if TState = "010" then
WR_n <= not Write;
end if;
end if;
if TState = "011" then
WR_n <= '1';
Expand Down

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