Skip to content
Permalink
Browse files

Merge "ODROID-XU3/4 : Adjust hdmi timing for 800x480p60hz to support …

…Vu5A" into odroidxu3-3.10.y-android
  • Loading branch information...
Joy Cho Gerrit Code Review
Joy Cho authored and Gerrit Code Review committed Nov 3, 2018
2 parents d330615 + f303fb5 commit cf366364c4773aed04943a145854ea7373b8d4db
@@ -1961,19 +1961,19 @@ static const struct hdmi_timings hdmi_conf_480x800p60 = {

static const struct hdmi_timings hdmi_conf_800x480p60 = {
.core = {
.h_blank = {0xc0, 0x00},
.v2_blank = {0xf3, 0x01},
.v1_blank = {0x13, 0x00},
.v_line = {0xf3, 0x01},
.h_line = {0xe0, 0x03},
.hsync_pol = {0x00},
.vsync_pol = {0x00},
.h_blank = {0x00, 0x01},
.v2_blank = {0x17, 0x02},
.v1_blank = {0x37, 0x00},
.v_line = {0x17, 0x02},
.h_line = {0x20, 0x04},
.hsync_pol = {0x01},
.vsync_pol = {0x01},
.int_pro_mode = {0x00},
.v_blank_f0 = {0xff, 0xff},
.v_blank_f1 = {0xff, 0xff},
.h_sync_start = {0x16, 0x00},
.h_sync_end = {0x5e, 0x00},
.v_sync_line_bef_2 = {0x0d, 0x00},
.h_sync_start = {0x2A, 0x00},
.h_sync_end = {0x82, 0x00},
.v_sync_line_bef_2 = {0x09, 0x00},
.v_sync_line_bef_1 = {0x03, 0x00},
.v_sync_line_aft_2 = {0xff, 0xff},
.v_sync_line_aft_1 = {0xff, 0xff},
@@ -2001,11 +2001,11 @@ static const struct hdmi_timings hdmi_conf_800x480p60 = {
},
.tg = {
0x00, /* cmd */
0xe0, 0x03, /* h_fsz */
0xc0, 0x00, 0x20, 0x03, /* hact */
0xf3, 0x01, /* v_fsz */
0x20, 0x04, /* h_fsz */
0x00, 0x01, 0x20, 0x03, /* hact */
0x17, 0x02, /* v_fsz */
0x01, 0x00, 0x33, 0x02, /* vsync */
0x13, 0x00, 0xe0, 0x01, /* vact */
0x37, 0x00, 0xE0, 0x01, /* vact */
0x33, 0x02, /* field_chg */
0x48, 0x02, /* vact_st2 */
0x7b, 0x04, /* vact_st3 */
@@ -48,6 +48,18 @@ static const u8 hdmiphy_conf27_027[32] = {
0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
};

/*
* To support Vu5A, pixel clock 33.9MHz is needed
* but we don't have the exact HDMI PHY table
* so as a workaround, the closest table will be used.
*/
static const u8 hdmiphy_conf33_9[32] = {
0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
};

static const u8 hdmiphy_conf40[32] = {
0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
@@ -187,7 +199,7 @@ const struct hdmiphy_conf hdmiphy_conf[] = {
{ V4L2_DV_BT_CEA_720X480P59_94, hdmiphy_conf27 },
{ V4L2_DV_BT_CEA_720X576P50, hdmiphy_conf27 },
{ V4L2_DV_BT_CEA_480X800P60, hdmiphy_conf32 },
{ V4L2_DV_BT_CEA_800X480P60, hdmiphy_conf32 },
{ V4L2_DV_BT_CEA_800X480P60, hdmiphy_conf33_9 },
{ V4L2_DV_BT_DMT_800X600P60, hdmiphy_conf40 },
{ V4L2_DV_BT_DMT_848X480P60, hdmiphy_conf31_49 },
{ V4L2_DV_BT_DMT_1024X600P60, hdmiphy_conf50_4 },
@@ -44,8 +44,9 @@

#define V4L2_DV_BT_CEA_800X480P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 480, 0, 0, \
32000000, 24, 72, 96, 3, 10, 6, 0, 0, 0, \
V4L2_INIT_BT_TIMINGS(800, 480, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
33900000, 44, 88, 124, 3, 6, 46, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}

0 comments on commit cf36636

Please sign in to comment.
You can’t perform that action at this time.