Some misc fixes #2607
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Some misc fixes #2607
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HiFiPhile
commented
Apr 23, 2024
| @@ -202,10 +202,10 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin | |||
| (xfer->max_size << DOEPCTL_MPSIZ_Pos); | |||
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| if (dir == TUSB_DIR_OUT) { | |||
| dwc2->epout[epnum].doepctl |= dxepctl; | |||
| dwc2->epout[epnum].doepctl = dxepctl; | |||
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dxepctl is not cleared on bus reset, besides no need to do masked write.
HiFiPhile
commented
Apr 23, 2024
| @@ -280,10 +280,17 @@ static void bus_reset(uint8_t rhport) { | |||
| dwc2->epout[n].doepctl |= DOEPCTL_SNAK; | |||
| } | |||
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| // 2. Disable all IN endpoints | |||
| for (uint8_t n = 0; n < ep_count; n++) { | |||
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If there are pending IN transfer on bus reset, eg. in cdc echo test do only write without read:
Since EPENA is not cleared on reset, once the EP is opened it will enter DIEPINT_TXFE interrupt and try to write packet and cause access violation.
HiFiPhile
commented
Apr 23, 2024
| @@ -700,11 +707,15 @@ void dcd_edpt_close_all(uint8_t rhport) { | |||
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| for (uint8_t n = 1; n < ep_count; n++) { | |||
| // disable OUT endpoint | |||
| dwc2->epout[n].doepctl = 0; | |||
| if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) { | |||
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Write dxepctl to 0 won't clear EPENA.
hathach
approved these changes
Apr 25, 2024
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Describe the PR
Some fixes I did when implementing dwc2 DMA support, better to do a separate PR.