Add defs.bzl for //synthesis package

README.md

@@ -66,7 +66,7 @@ This is the `BUILD` file. Every thing in bazel needs a rule description of what
 to build. The rules use yosys and OpenROAD to place and route your design.
 
 ```python
-load("@rules_hdl//synthesis:build_defs.bzl", "synthesize_rtl")
+load("@rules_hdl//synthesis:defs.bzl", "synthesize_rtl")
 load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route")
 load("@rules_hdl//verilog:defs.bzl", "verilog_library")
 

flows/basic_asic.bzl

@@ -18,7 +18,7 @@ load("@bazel_skylib//rules:build_test.bzl", "build_test")
 load("//gds_write:build_defs.bzl", "gds_write")
 load("//place_and_route:build_defs.bzl", "place_and_route")
 load("//static_timing:build_defs.bzl", "run_opensta")
-load("//synthesis:build_defs.bzl", "synthesize_rtl")
+load("//synthesis:defs.bzl", "synthesize_rtl")
 
 def _get_with_defaults(target_name, extra_args, defaults):
     target_extra_args = dict(**extra_args.pop(target_name, {}))

gds_write/build_defs.bzl

@@ -16,7 +16,7 @@
 
 load("@rules_hdl//pdk:open_road_configuration.bzl", "assert_has_open_road_configuration", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def _gds_write_impl(ctx):
     # Throws an error if there is no OpenROAD configuration

place_and_route/build_defs.bzl

@@ -27,7 +27,7 @@ load("//place_and_route:private/pdn_gen.bzl", "pdn_gen")
 load("//place_and_route:private/place_pins.bzl", "place_pins")
 load("//place_and_route:private/repair.bzl", "repair")
 load("//place_and_route:private/resize.bzl", "resize")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 PLACE_AND_ROUTE_STEPS = [
     ("init_floor_plan", init_floor_plan, "pre_pnr"),

place_and_route/open_road.bzl

@@ -14,8 +14,8 @@
 
 """File encapsulating the open road command"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 OpenRoadInfo = provider(
     "Provider to support running openroad outside of bazel",

place_and_route/private/clock_tree_synthesis.bzl

@@ -14,9 +14,9 @@
 
 """Clock Tree Synthesis openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "format_openroad_do_not_use_list", "merge_open_road_info", "openroad_command", "placement_padding_commands", "timing_setup_commands")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def clock_tree_synthesis(ctx, open_road_info):
     """Performs clock tree synthesis.

place_and_route/private/detailed_routing.bzl

@@ -14,9 +14,9 @@
 
 """Detailed Routing openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "DetailedRoutingInfo", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "DetailedRoutingInfo", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def detailed_routing(ctx, open_road_info):
     """Performs detailed routing.

place_and_route/private/floorplan.bzl

@@ -14,11 +14,11 @@
 
 """Floorplaning openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "openroad_command", "timing_setup_commands")
 load("//place_and_route:private/report_area.bzl", "generate_area_results")
 load("//place_and_route:private/report_power.bzl", "generate_power_results")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def _initialize_floorplan_command(ctx):
     open_road_configuration = get_open_road_configuration(ctx.attr.synthesized_rtl[SynthesisInfo])

place_and_route/private/global_placement.bzl

@@ -14,9 +14,9 @@
 
 """Global placement openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def global_placement(ctx, open_road_info):
     """Performs the global placement of the standard cells.

place_and_route/private/global_routing.bzl

@@ -14,11 +14,11 @@
 
 """Global Routing openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
 load("//place_and_route:private/report_area.bzl", "generate_area_results")
 load("//place_and_route:private/report_power.bzl", "generate_power_results")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def _global_routing_layer_adjustments(adjustments):
     adjustment_command = "{"

place_and_route/private/pdn_gen.bzl

@@ -14,9 +14,9 @@
 
 """PDN openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def pdn_gen(ctx, open_road_info):
     """Generates the power delivery network for the ASIC.

place_and_route/private/place_pins.bzl

@@ -14,9 +14,9 @@
 
 """Pin Placement openROAD commands"""
 
-load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
+load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def place_pins(ctx, open_road_info):
     """Places pins around the die area.

place_and_route/private/repair.bzl

@@ -16,7 +16,7 @@
 
 load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
 load("//place_and_route:open_road.bzl", "OpenRoadInfo", "format_openroad_do_not_use_list", "merge_open_road_info", "openroad_command", "timing_setup_commands")
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def repair(ctx, open_road_info):
     """Performs several repair operations on a placed design.

place_and_route/private/report_power.bzl

@@ -14,7 +14,7 @@
 
 """Report Power Commands"""
 
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def generate_power_results(ctx, output_file):
     netlist_target = ctx.attr.synthesized_rtl

static_timing/build_defs.bzl

@@ -14,7 +14,7 @@
 
 """Rules for running openSTA on synthesized Verilog."""
 
-load("//synthesis:build_defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SynthesisInfo")
 
 def _run_opensta_impl(ctx):
     """Implementation of the 'run_opensta' rule.

synthesis/build_defs.bzl

@@ -37,14 +37,14 @@ ExternalSynthesisInfo = provider(
     },
 )
 
-# Args:
-#    standard_cell_info: The StandardCellInfo provider this target was synthesized against.
-#    synthesized_netlist: The structural verilog syntheized with standard_cell_info
-#    top_module: The name of the top level module of the synthesized netlist
-#    log_file: Log output file from the synthesis step.
 SynthesisInfo = provider(
     "Information about the synthesis target",
-    fields = ["standard_cell_info", "synthesized_netlist", "top_module", "log_file"],
+    fields = {
+        "log_file": "Log output file from the synthesis step.",
+        "standard_cell_info": "The StandardCellInfo provider this target was synthesized against.",
+        "synthesized_netlist": "he structural verilog syntheized with standard_cell_info",
+        "top_module": "The name of the top level module of the synthesized netlist",
+    },
 )
 
 def _transitive_srcs(deps):
@@ -294,7 +294,9 @@ def _synthesize_binary_impl(ctx):
 synthesis_binary = rule(
     implementation = _synthesize_binary_impl,
     attrs = {
-        "synthesize_rtl_rule": attr.label(providers = [ExternalSynthesisInfo]),
+        "synthesize_rtl_rule": attr.label(
+            providers = [ExternalSynthesisInfo],
+        ),
         "yosys_tool": attr.label(
             default = Label("@at_clifford_yosys//:yosys"),
             executable = True,
@@ -316,9 +318,15 @@ synthesize_rtl = rule(
             allow_single_file = True,
             doc = "Verilog file that maps yosys adder to PDK adders.",
         ),
-        "deps": attr.label_list(providers = [[VerilogInfo], [UhdmInfo]]),
-        "output_file_name": attr.string(doc = "The output file name."),
-        "srcs": attr.label_list(allow_files = True),
+        "deps": attr.label_list(
+            providers = [[VerilogInfo], [UhdmInfo]],
+        ),
+        "output_file_name": attr.string(
+            doc = "The output file name.",
+        ),
+        "srcs": attr.label_list(
+            allow_files = True,
+        ),
         "standard_cells": attr.label(
             providers = [StandardCellInfo],
             default = "@com_google_skywater_pdk_sky130_fd_sc_hd//:sky130_fd_sc_hd",
@@ -328,8 +336,12 @@ synthesize_rtl = rule(
             allow_single_file = True,
             doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl",
         ),
-        "target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"),
-        "top_module": attr.string(default = "top"),
+        "target_clock_period_pico_seconds": attr.int(
+            doc = "target clock period in picoseconds",
+        ),
+        "top_module": attr.string(
+            default = "top",
+        ),
         "yosys_tool": attr.label(
             default = Label("@at_clifford_yosys//:yosys"),
             executable = True,

synthesis/defs.bzl

@@ -0,0 +1,18 @@
+"""Rules for synthesizing (System)Verilog code."""
+
+load(
+    ":build_defs.bzl",
+    _ExternalSynthesisInfo = "ExternalSynthesisInfo",
+    _SynthesisInfo = "SynthesisInfo",
+    _UhdmInfo = "UhdmInfo",
+    _benchmark_synth = "benchmark_synth",
+    _synthesis_binary = "synthesis_binary",
+    _synthesize_rtl = "synthesize_rtl",
+)
+
+benchmark_synth = _benchmark_synth
+ExternalSynthesisInfo = _ExternalSynthesisInfo
+synthesis_binary = _synthesis_binary
+SynthesisInfo = _SynthesisInfo
+synthesize_rtl = _synthesize_rtl
+UhdmInfo = _UhdmInfo

tests/BUILD

@@ -19,7 +19,7 @@ load("//flows:basic_asic.bzl", "basic_asic_flow")
 load("//gds_write:build_defs.bzl", "gds_write")
 load("//place_and_route:build_defs.bzl", "place_and_route")
 load("//static_timing:build_defs.bzl", "run_opensta")
-load("//synthesis:build_defs.bzl", "synthesize_rtl")
+load("//synthesis:defs.bzl", "synthesize_rtl")
 load("//verilog:defs.bzl", "verilog_library")
 
 package(