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Merge pull request #1283 from stlankes/toolchain
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switch to the lastest nightly compiler
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stlankes committed Jun 18, 2024
2 parents ad9bdc1 + a9a7906 commit 2143b3b
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Showing 5 changed files with 14 additions and 8 deletions.
2 changes: 1 addition & 1 deletion rust-toolchain.toml
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[toolchain]
channel = "nightly-2024-06-01"
channel = "nightly-2024-06-18"
components = [
"llvm-tools",
"rust-src",
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8 changes: 5 additions & 3 deletions src/arch/riscv64/kernel/scheduler.rs
Original file line number Diff line number Diff line change
Expand Up @@ -160,7 +160,8 @@ impl TaskStacks {
unsafe {
ptr::write_bytes(
(virt_addr
+ KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
+ KERNEL_STACK_SIZE
+ DEFAULT_STACK_SIZE
+ 3 * BasePageSize::SIZE as usize)
//(virt_addr + KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE)
.as_mut_ptr::<u8>(),
Expand Down Expand Up @@ -198,7 +199,8 @@ impl TaskStacks {
TaskStacks::Boot(_) => VirtAddr::zero(),
TaskStacks::Common(stacks) => {
stacks.virt_addr
+ KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
+ KERNEL_STACK_SIZE
+ DEFAULT_STACK_SIZE
+ 3 * BasePageSize::SIZE as usize
//stacks.virt_addr + KERNEL_STACK_SIZE + DEFAULT_STACK_SIZE
}
Expand Down Expand Up @@ -280,7 +282,7 @@ impl TaskTLS {
// Yes, it does, so we have to allocate TLS memory.
// Allocate enough space for the given size and one more variable of type usize, which holds the tls_pointer.
let tls_allocation_size = tls_size.align_up(32usize); // + mem::size_of::<usize>();
// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
// We allocate in 128 byte granularity (= cache line size) to avoid false sharing
let memory_size = tls_allocation_size.align_up(128usize);
let layout =
Layout::from_size_align(memory_size, 128).expect("TLS has an invalid size / alignment");
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3 changes: 2 additions & 1 deletion src/arch/x86_64/kernel/apic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -825,7 +825,8 @@ pub fn ipi_tlb_flush() {
local_apic_write(
IA32_X2APIC_ICR,
destination
| APIC_ICR_LEVEL_ASSERT | APIC_ICR_DELIVERY_MODE_FIXED
| APIC_ICR_LEVEL_ASSERT
| APIC_ICR_DELIVERY_MODE_FIXED
| u64::from(TLB_FLUSH_INTERRUPT_NUMBER),
);
}
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3 changes: 2 additions & 1 deletion src/drivers/pci.rs
Original file line number Diff line number Diff line change
Expand Up @@ -283,7 +283,8 @@ impl<T: ConfigRegionAccess> fmt::Display for PciDevice<T> {
};

#[cfg(not(feature = "pci-ids"))]
let (class_name, vendor_name, device_name) = ("Unknown Class", "Unknown Vendor", "Unknown Device");
let (class_name, vendor_name, device_name) =
("Unknown Class", "Unknown Vendor", "Unknown Device");

// Output detailed readable information about this device.
write!(
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6 changes: 4 additions & 2 deletions src/fd/socket/tcp.rs
Original file line number Diff line number Diff line change
Expand Up @@ -172,8 +172,10 @@ impl ObjectInterface for Socket {
self.with(|socket| match socket.state() {
tcp::State::Closed | tcp::State::Closing | tcp::State::CloseWait => {
let available = PollEvent::POLLOUT
| PollEvent::POLLWRNORM | PollEvent::POLLWRBAND
| PollEvent::POLLIN | PollEvent::POLLRDNORM
| PollEvent::POLLWRNORM
| PollEvent::POLLWRBAND
| PollEvent::POLLIN
| PollEvent::POLLRDNORM
| PollEvent::POLLRDBAND;

let ret = event & available;
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