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Welcome to the CoPro6502 wiki!
A family of designs for the Matchbox Co Pro for the BBC Micro.
For more details on the designs, see:
http://stardot.org.uk/forums/viewtopic.php?t=8852&f=44
The Signposts Thread has a some well organized information (thanks Paul!):
http://stardot.org.uk/forums/viewtopic.php?f=3&t=9994
The User Survey Thread has some user feed back on the first batch of boards:
http://www.stardot.org.uk/forums/viewtopic.php?f=3&t=9898
For Jason's LX9 Hardware, see:
http://stardot.org.uk/forums/viewtopic.php?t=8932&f=8 and http://www.xeropage.co.uk/shop/index.php?id_product=13&controller=product
There have been 4 batches of boards:
- Prototype - November 2014 (2 units?)
- Batch 1 - December 2014 (40 units?) (Red boards, firmware build from commit 7f98d5ad)
- Batch 2 - December 2015 (50 units?) (Green boards, 20151215_1004 firmware)
- Batch 3 - September 2016 (20 units?) (Green boards, 20151215_1004 firmware)
- Batch 4 - December 2016 (20 units?) (Green boards, 20151215_1004 firmware)
- master - this is now the current branch again as of 28/02/2016**.
- ns32k - this branch was used for development of the 32016 Co Pro and was merged back to master 28/02/2016
- synctube - this branch started 14/02/2015 and was merged back to master 15/11/2015 and is now obsolete. It was where we did the work to move from Ed/Rich's original Tube code (with a few fixes) to the new fully synchronous Tube design. The issue with the old code was that it relied on SR-latches to implement the FIFO flag logic that spanned the two clock domains. Some FPGAs (e.g. Spartan 6) do not have a native implementation of an SR-latch. The synctube work replaces the FIFO flag logic with a more FPGA friendly synchronous design that only uses D-type registers.
- tubeclken - this branch is parking some experimental code that is now obsolete.
**If building any of the Co Pro designs, you should use the master branch.
The latest Xilinx firmware (built from the master branch) is:
https://github.com/hoglet67/CoPro6502/releases/tag/20171007_0719
The is the point in the stardot thread where the latest firmware was released:
http://www.stardot.org.uk/forums/viewtopic.php?p=182115#p182115
These reflect firmware LX9CoProCombined_20171007_0719_dmb
The settings for older versions of the firmware can be found here:
- LX9CoProCombined_20161110_1455_dmb
- LX9CoProCombined_20160228_1555_dmb
- LX9CoProCombined_20151215_1004_dmb
- LX9CoProCombined_20151115_1858_dmb
- LX9CoProCombined_20150901_1358_dmb
- LX9CoProCombined_20150819_1109_dmb
- LX9CoProCombined_20150328_1656_dmb
The above multi-boot firmware selects the CoPro design to boot as follows:
| N | 1 2 3 4 | Design | RAM | Core |
|---|---|---|---|---|
| 0 | 0 0 0 0 | 3MHz 65C102 | 64KB internal + 1MB external RAM | 65C02 port of Arlet's core |
| 1 | 0 0 0 1 | 4MHz 65C102 | 64KB internal + 1MB external RAM | 65C02 port of Arlet's core |
| 2 | 0 0 1 0 | 16MHz 65C102 | 64KB internal + 1MB external RAM | 65C02 port of Arlet's core |
| 3 | 0 0 1 1 | 64MHz 65C102 | 64KB internal + 1MB external RAM | 65C02 port of Arlet's core |
| 4 | 0 1 0 0 | 8MHz Z80 | 64KB external RAM | T80 core |
| 5 | 0 1 0 1 | 32MHz Z80 | 64KB internal RAM | NextZ80 core |
| 6 | 0 1 1 0 | 56MHz Z80 | 64KB internal RAM | NextZ80 core |
| 7 | 0 1 1 1 | 112MHz Z80 | 64KB internal RAM | NextZ80 core |
| 8 | 1 0 0 0 | 12Mhz 80286 | 896KB external RAM | Zet core |
| 9 | 1 0 0 1 | 4MHz 6809 | 64KB external RAM | SYS09 core |
| 10 | 1 0 1 0 | 16MHz 68000 | 1MB external RAM | TG68 core |
| 11 | 1 0 1 1 | 32MHz PDP11 | 64KB internal RAM | PDP2011 core |
| 12 | 1 1 0 0 | 32MHz ARM2 | 2MB external RAM | Amber23 core |
| 13 | 1 1 0 1 | 32MHz 32016 | 2MB external RAM | m32632 core |
| 14 | 1 1 1 0 | Null / SPI | Raspberry Pi soft core | |
| 15 | 1 1 1 1 | BIST |
Note about the above table:
- DIP switch (1) is furthest away from the tube connector
- DIP switch (4) is nearest the tube connector
- A "0" is generate when the DIP switch is ON (the corresponding input is connected by the switch to 0V)
- A "1" is generate when the DIP switch is OFF (the corresponding input pulled up to 3V3 through a resistor)
There has been lots of confusion on the forum as to whether "0" is towards or away from the Xilinx. I think it's possible the DIP switch has not been mounted consistently. At least on my board, one side of the DIP switch is labelled "on"; that side corresponds to "0" in the above table.
In version "LX9CoProCombined_20150901_1358_dmb", the ability to switch between Co Processors in was added, and disable the Co Processor was added.
To switch, use *FX 151,230,N (see above table) and then press Ctrl-Break.
If the DIP switches are changes on a running system, the Co Processor will be reconfigured on the next Break.
There is 1MByte of external RAM available, if the Matchbox board is fully populated. That's half the physical memory, for technical reasons. The 6502 memory map is spilt into 8K pages using a set of eight (write-only) paging registers at &FEE0-&FEE7:
- the register at &FEE0 controls the mapping of 0x0000-0x1FFF
- the register at &FEE1 controls the mapping of 0x2000-0x3FFF, etc
- page values of 0x00-0x07 are directed to fast internal block RAM (and this is the default).
- page values of 0x80-0xFF are directed to slower external static RAM.
Note that the I/O space in 6502 page &FE is always present. All other RAM space is paged, including page &FF with the vectors, page zero and the stack page, and including the OS in the top 4k. Page these out only with suitable preparation.