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The FPGA used in this design has a feature where multiple designs can be held in the serial SPI Flash chip that configures the FPGA at power on. This allows the FPGA to select one of many second processor designs based on the on-board 4 way DIP switch or by entering a command on the host computer and restarting it.
The board also has two 74LVC4245APW level translating buffers to convert between the 5V logic levels of the Tube interface and the 3.3V Logic levels of the IO of the FPGA.
The board is supplied with 5V from the tube connector and the LTC3419EMS switching regulator supplies the 3.3V and 1.2V power rails needed for the other devices.
For a complete history see this Forum Thread.
Circuit Diagram (Schematic) and Layout here.