Merge pull request #18637 from unknownbrackets/riscv-more

Add some more RISC-V extensions to emitter
hrydgard · Dec 29, 2023 · 46b25d2 · 46b25d2
2 parents 5c1767c + 52db66e
commit 46b25d2
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Showing 9 changed files with 650 additions and 58 deletions.
diff --git a/Common/CPUDetect.h b/Common/CPUDetect.h
@@ -114,6 +114,13 @@ struct CPUInfo {
 	bool RiscV_Zbb;
 	bool RiscV_Zbc;
 	bool RiscV_Zbs;
+	bool RiscV_Zcb;
+	bool RiscV_Zfa;
+	bool RiscV_Zfh;
+	bool RiscV_Zfhmin;
+	bool RiscV_Zicond;
+	bool RiscV_Zvbb;
+	bool RiscV_Zvkb;
 
 	// LoongArch specific extension flags.
 	bool LOONGARCH_CPUCFG;

diff --git a/Common/RiscVCPUDetect.cpp b/Common/RiscVCPUDetect.cpp
@@ -241,10 +241,17 @@ std::vector<std::string> CPUInfo::Features() {
 		{ RiscV_D, "Double" },
 		{ RiscV_C, "Compressed" },
 		{ RiscV_V, "Vector" },
+		{ RiscV_Zvbb, "Vector Basic Bitmanip" },
+		{ RiscV_Zvkb, "Vector Crypto Bitmanip" },
 		{ RiscV_Zba, "Bitmanip Zba" },
 		{ RiscV_Zbb, "Bitmanip Zbb" },
 		{ RiscV_Zbc, "Bitmanip Zbc" },
 		{ RiscV_Zbs, "Bitmanip Zbs" },
+		{ RiscV_Zcb, "Compress Zcb" },
+		{ RiscV_Zfa, "Float Additional" },
+		{ RiscV_Zfh, "Float Half" },
+		{ RiscV_Zfhmin, "Float Half Minimal" },
+		{ RiscV_Zicond, "Integer Conditional" },
 		{ RiscV_Zicsr, "Zicsr" },
 		{ CPU64bit, "64-bit" },
 	};