riscv: Cleanup missing Poison, Crash.

hrydgard · Feb 12, 2023 · 89c18d8 · 89c18d8
1 parent 0532b35
commit 89c18d8
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Showing 7 changed files with 29 additions and 3 deletions.
diff --git a/Common/CommonFuncs.h b/Common/CommonFuncs.h
@@ -36,6 +36,8 @@
 #define Crash() {asm ("bkpt #0");}
 #elif PPSSPP_ARCH(ARM64)
 #define Crash() {asm ("brk #0");}
+#elif PPSSPP_ARCH(RISCV64)
+#define Crash() {asm ("ebreak");}
 #else
 #include <signal.h>
 #define Crash() {kill(getpid(), SIGINT);}

diff --git a/Common/RiscVEmitter.cpp b/Common/RiscVEmitter.cpp
@@ -4278,4 +4278,16 @@ void RiscVEmitter::C_SDSP(RiscVReg rs2, u32 uimm9) {
 	Write16(EncodeCSS(Opcode16::C2, rs2, imm5_4_3_8_7_6, Funct3::C_SDSP));
 }
 
+void RiscVCodeBlock::PoisonMemory(int offset) {
+	// So we can adjust region to writable space.  Might be zero.
+	ptrdiff_t writable = writable_ - code_;
+
+	u32 *ptr = (u32 *)(region + offset + writable);
+	u32 *maxptr = (u32 *)(region + region_size - offset + writable);
+	// This will only write an even multiple of u32, but not much else to do.
+	// RiscV: 0x00100073 = EBREAK
+	while (ptr < maxptr)
+		*ptr++ = 0x00100073;
+}
+
 };
diff --git a/Common/RiscVEmitter.h b/Common/RiscVEmitter.h
@@ -47,6 +47,8 @@ enum RiscVReg {
 	V8, V9, V10, V11, V12, V13, V14, V15,
 	V16, V17, V18, V19, V20, V21, V22, V23,
 	V24, V25, V26, V27, V28, V29, V30, V31,
+
+	INVALID_REG = 0xFFFFFFFF,
 };
 
 enum class FixupBranchType {
@@ -1024,13 +1026,14 @@ class RiscVEmitter {
 		writable_ += 2;
 	}
 
+protected:
 	const u8 *code_ = nullptr;
 	u8 *writable_ = nullptr;
 	const u8 *lastCacheFlushEnd_ = nullptr;
 	bool autoCompress_ = false;
 };
 
-class MIPSCodeBlock : public CodeBlock<RiscVEmitter> {
+class RiscVCodeBlock : public CodeBlock<RiscVEmitter> {
 private:
 	void PoisonMemory(int offset) override;
 };

diff --git a/Core/MIPS/JitCommon/JitBlockCache.cpp b/Core/MIPS/JitCommon/JitBlockCache.cpp
@@ -698,7 +698,7 @@ JitBlockDebugInfo JitBlockCache::GetBlockDebugInfo(int blockNum) const {
 	debugInfo.targetDisasm = DisassembleArm64(block->normalEntry, block->codeSize);
 #elif PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
 	debugInfo.targetDisasm = DisassembleX86(block->normalEntry, block->codeSize);
-#elif PPSSPP_ARCH(ARM64)
+#elif PPSSPP_ARCH(RISCV64)
 	debugInfo.targetDisasm = DisassembleRV64(block->normalEntry, block->codeSize);
 #endif
 

diff --git a/Core/MIPS/JitCommon/JitState.cpp b/Core/MIPS/JitCommon/JitState.cpp
@@ -60,7 +60,7 @@ namespace MIPSComp {
 
 		useStaticAlloc = false;
 		enablePointerify = false;
-#if PPSSPP_ARCH(ARM64)
+#if PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(RISCV64)
 		useStaticAlloc = !Disabled(JitDisable::STATIC_ALLOC);
 		// iOS/etc. may disable at runtime if Memory::base is not nicely aligned.
 		enablePointerify = !Disabled(JitDisable::POINTERIFY);

diff --git a/GPU/Software/RasterizerRegCache.cpp b/GPU/Software/RasterizerRegCache.cpp
@@ -145,6 +145,8 @@ void RegCache::SetupABI(const std::vector<Purpose> &args, bool forceRetain) {
 	for (Reg r : vecTemps)
 		Add(r, VEC_INVALID);
 #endif
+#elif PPSSPP_ARCH(RISCV64)
+	_assert_msg_(false, "Not yet implemented (no vector calling standard yet)");
 #elif PPSSPP_ARCH(MIPS)
 	_assert_msg_(false, "Not yet implemented");
 #else

diff --git a/GPU/Software/RasterizerRegCache.h b/GPU/Software/RasterizerRegCache.h
@@ -44,6 +44,8 @@
 #include "Common/x64Emitter.h"
 #elif PPSSPP_ARCH(MIPS)
 #include "Common/MipsEmitter.h"
+#elif PPSSPP_ARCH(RISCV64)
+#include "Common/RiscVEmitter.h"
 #else
 #include "Common/FakeEmitter.h"
 #endif
@@ -60,6 +62,8 @@ typedef Arm64Gen::ARM64CodeBlock BaseCodeBlock;
 typedef Gen::XCodeBlock BaseCodeBlock;
 #elif PPSSPP_ARCH(MIPS)
 typedef MIPSGen::MIPSCodeBlock BaseCodeBlock;
+#elif PPSSPP_ARCH(RISCV64)
+typedef RiscVGen::RiscVCodeBlock BaseCodeBlock;
 #else
 typedef FakeGen::FakeXCodeBlock BaseCodeBlock;
 #endif
@@ -169,6 +173,9 @@ struct RegCache {
 #elif PPSSPP_ARCH(MIPS)
 	typedef MIPSGen::MIPSReg Reg;
 	static constexpr Reg REG_INVALID_VALUE = MIPSGen::INVALID_REG;
+#elif PPSSPP_ARCH(RISCV64)
+	typedef RiscVGen::RiscVReg Reg;
+	static constexpr Reg REG_INVALID_VALUE = RiscVGen::INVALID_REG;
 #else
 	typedef int Reg;
 	static constexpr Reg REG_INVALID_VALUE = -1;