[nine][shader] Guild Wars 2 with Shaders on "medium" #303

siro20 · 2018-01-29T13:56:44Z

The grass has some weird blue on radeonsi / llvmpipe. It doesn't happen on wine. Looks like a shader is faulty.

siro20 · 2018-02-25T10:25:29Z

Looks like the vertex shader is broken, as the vertex/texture has a slight offset. It doesn't overlap with the previous calculated lightmap, causing the blue artifacts.

axeldavy · 2018-03-04T10:14:26Z

Do you happen to have a trace ?

siro20 · 2018-03-06T18:43:48Z

Uploaded on our FTP: Gw2-64.5.trace.xz

axeldavy · 2018-03-10T13:50:36Z

Fixed

Stateblocks with NINESBT_ALL should track all textures. For better performance they have a faster path which copies all the states where required. This path was only tracking ps textures. Fixes: #303 Signed-off-by: Axel Davy <axel.davy@ens.fr>

Stateblocks with NINESBT_ALL should track all textures. For better performance they have a faster path which copies all the required. This path was only tracking ps textures. Fixes: iXit/Mesa-3D#303 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 71eae79)

Stateblocks with NINESBT_ALL should track all textures. For better performance they have a faster path which copies all the required. This path was only tracking ps textures. Fixes: iXit/Mesa-3D#303 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> cherry-applies: 71eae79

Stateblocks with NINESBT_ALL should track all textures. For better performance they have a faster path which copies all the required. This path was only tracking ps textures. Fixes: iXit/Mesa-3D#303 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 71eae79)

* Update external/mesa3d from branch 'master' to b72dd1fbdd1bd24e47360131c5931cb69ffe44ca - Merge "Android.bp: define HAVE_TIMESPEC_GET" - Android.bp: define HAVE_TIMESPEC_GET Since https://android-review.googlesource.com/c/718518 added timespec_get() to bionic, mesa3d doesn't build due to redefinition of timespec_get(). Avoid redefinition by defining HAVE_TIMESPEC_GET flag. Test: build and boot tested db820c to UI. Change-Id: I3dcc8034b48785e45cd3fa50e4d9cf2c684694a0 Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> - Merge "Convert implicit rules to static pattern rules" - Convert implicit rules to static pattern rules We're deprecating make implicit rules, preferring static pattern rules, or just regular rules. Test: diff build-aosp_dragon.ninja Change-Id: I450cd49789fe380de20364b45abe8282f84b98c2 - Merge "Fix checkbuild on Mac builders." - Fix checkbuild on Mac builders. The libmesa_dri_common target depends on xgettext unconditionally, but this is not a documented dependency of AOSP and is not installed on the Mac builders, so we must not build any part of mesa3d on these platforms. Bug: 79909534 Bug: 79165890 Change-Id: Ice7129f046ca823e80132e34911c9bb8f1226b4c Signed-off-by: Alistair Strachan <astrachan@google.com> - Merge changes from topic "mesa3d_18" * changes: Merge branch 'aosp/upstream-18.0' Add xf86drm.h wrapper with pending features. - Merge branch 'aosp/upstream-18.0' Squashes down these Change-Ids: I73eeba6dabfa83a4404c8371ae39ad0c26b73102 Ica4a80c917beb990b5df18f9bee591ce3cfc9f42 Bug: 79165890 Change-Id: Iec064b10e8ea5a08d57e8660bc9f6a7fb35d02da Signed-of-by: Alistair Strachan <astrachan@google.com> - Add xf86drm.h wrapper with pending features. Fork of a libdrm change so we can move forward with a mesa3d merge without needing to update libdrm again. From: Robert Foss <robert.foss@collabora.com> drmHandleMatch is intended to allow for userspace to filter out devices that it does not want to open. Opening specific devices using paths alone is not a reliable due to probing order. This function intends to provide a mechanism for filtering out devices that don't fit what you need using an extensible set of filters. drm_match_key_t is intended to be extended with whatever filter that would come in handy down the line. As a catch-all filter, the DRM_MATCH_FUNCTION was included which allows the caller to filter based on an arbitrary function. An function pointer filter could of course filter based on anything. But for the sake of convenience a few other simple filters have been included. If the function pointer filter ends up being called with a boilerplate fp by mutliple libdrm users, perhaps that funtion could be moved into libdrm at a future date. Signed-off-by: Robert Foss <robert.foss@collabora.com> [astrachan: cherry picked pending upstream change to resolve merge issue] Bug: 79165890 List: https://patchwork.kernel.org/patch/10368203/ Change-Id: I2d3e6e0e85e5ac0d3039051078d7df9abb36e126 Signed-off-by: Alistair Strachan <astrachan@google.com> - Merge "Add metadata files" - radeon/vcn: fix mpeg4 msg buffer settings Previous bit-fields assignments are incorrect and will result certain mpeg4 decode failed due to wrong flag values. This patch fixes these assignments. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (cherry picked from commit deba56accf4e1f8fc025f34f6cbc069285f76838) - i965/tex_image: Avoid the ASTC LDR workaround on gen9lp Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <eero.t.tamminen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 3e56e4642fb5875b3f5c4eb34798ba9f3d827705) - radv: compute the number of subpass attachments correctly Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit d8db5986cee83078e46895d695d698db87507019) - radv/winsys: fix leaking resources from bo's imported by fd A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit f56e22e49673e8234a7fe0c241b4c3eae4752f34) - Add metadata files Change-Id: I6d976aa8d8adac4af4b7cae8a8b4d93a21202465 - st/omx/enc: fix blit setup for YUV LoadImage The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses the second half as source. Currently we use "1" as the start point of x for R, then causing 1 source pixel of U component shift to right. So "-1" should be the start point for U component. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 1c5f4f4e17f74d823d9e38c678e40e9f49e2c053) [Juan A. Suarez: apply patch in src/gallium/state_trackers/omx_bellagio/vid_enc.c] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/gallium/state_trackers/omx/vid_enc_common.c - gallium/util: Fix incorrect refcounting of separate stencil. The driver may have a reference on the separate stencil buffer for some reason (like an unflushed job using it), so we can't directly free the resource and should instead just decrement the refcount that we own. Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8 on vc5. Fixes: e94eb5e6000e ("gallium/util: add u_transfer_helper") Reviewed-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 069c409f434ab215940aad2092d5d236b410a7b9) - radeonsi/gfx9: workaround for INTERP with indirect indexing and clean up the conditions. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 6d19120da851c0d3f97376c733d674f7c8ab0457) - util/u_queue: fix a deadlock in util_queue_finish Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 7083ac7290a0c37a45494437a45441112f3cc36c) - anv/allocator: Don't shrink either end of the block pool Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147 Tested-by: Eero Tamminen <eero.t.tamminen@intel.com> Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 3db93f9128e5329f6658c9018cf23eb31807c24c) - cherry-ignore: add explicit 18.1 only nominations Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: add sha256 checksums for 18.0.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: add release notes for 18.0.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Update version to 18.0.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Merge "Add myself and Dmitry to OWNERS." - Add myself and Dmitry to OWNERS. Bug: 78634016 Change-Id: Icd360ef71e8eaff5931dd01f7ff27ac477c88806 - Merge "Add option to use vendor version of mesa" - meson: don't build classic mesa tests without dri_drivers Since mesa_classic is build-on-demand the tests will create a demand and add a bunch of extra compilation. Fixes: 43a6e84927e3b1290f6f211f5dfb184dfe5a719e ("meson: build mesa test.") Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit aaab6242456a4a5e737da0add179704b0b6f3676) - radv/winsys: allow to submit up to 4 IBs for chips without chaining The SI family doesn't support chaining which means the maximum size in dwords per CS is limited. When that limit was reached we failed to submit the CS and the application crashed. This patch allows to submit up to 4 IBs which is currently the limit, but recent amdgpu supports more than that. Please note that we can reach the limit of 4 IBs per submit but currently we can't improve that. The only solution is to upgrade libdrm. That will be improved later but for now this should fix crashes on SI or when using RADV_DEBUG=noibs. Fixes: 36cb5508e89 ("radv/winsys: Fail early on overgrown cs.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105775 Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> - intel/compiler: Add scheduler deps for instructions that implicitly read g0 Otherwise the scheduler can move the writes after the reads. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Mark Janes <mark.a.janes@intel.com> Cc: Clayton A Craft <clayton.a.craft@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 0d5ce25c1ca23abc6d91538f4374a18509091060) - Add option to use vendor version of mesa bug: 70165141 Test: Local build Merged-In: I7f9de1b818cbeb474020424b79a7128a40c779a6 Change-Id: I7f9de1b818cbeb474020424b79a7128a40c779a6 Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com> Signed-off-by: Yong Yao <yong.yao@intel.com> (cherry picked from commit 980ddb1b9b6ac19a66f431a6cff3bc469fa2e3b9) - bin/install_megadrivers: fix DESTDIR and -D*-path This fixes -Ddri-drivers-path, -Dvdpau-libs-path, etc. with DESTDIR when those paths are absolute. Currently due to the way python's os.path.join handles absolute paths these will ignore DESTDIR, which is bad. This fixes them to be relative to DESTDIR if that is set. Fixes: 3218056e0eb375eeda470058d06add1532acd6d4 ("meson: Build i965 and dri stack") Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> (cherry picked from commit ae3f45c11e3f934939b90445471da8f18b057bc5) - Revert "st/dri: Fix dangling pointer to a destroyed dri_drawable" This reverts commit dab02dea3411d325a5aee6cda5b581e61396ecc6. It causes crashes of qtcreator and firefox. Fixes: dab02de "st/dri: Fix dangling pointer to a destroyed dri_drawable" Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 4559aefb5cee5878198f8491680abe47df3e3250) - i965/fs: Return mlen * 8 for size_read() for INTERPOLATE_AT_* They are send messages and this makes size_read() and mlen agree. For both of these opcodes, the payload is just a dummy so mlen == 1 and this should decrease register pressure a bit. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit de1f22d595d40f6c2e2d80db73aa90d62a875de5) - cherry-ignore: add explicit 18.1 only nominations Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - st/dri: Fix dangling pointer to a destroyed dri_drawable If an EGLSurface is created, made current and destroyed, and then a second EGLSurface is created. Then the second malloc in driCreateNewDrawable may return the same pointer address the first surface's drawable had. Consequently, when dri_make_current later tries to determine if it should update the texture_stamp it compares the surface's drawable pointer against the drawable in the last call to dri_make_current and assumes it's the same surface (which it isn't). When texture_stamp is left unset, then dri_st_framebuffer_validate thinks it has already called update_drawable_info for that drawable, leaving it unvalidated and this is when bad things starts to happen. In my case it manifested itself by the width and height of the surface being unset. This is fixed this by setting the pointer to NULL before freeing the surface. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106126 Signed-off-by: Johan Klokkhammer Helsing <johan.helsing@qt.io> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit dab02dea3411d325a5aee6cda5b581e61396ecc6) - etnaviv: fix texture_format_needs_swiz memcmp returns 0 when both swizzles are the same, which means we don't need any hardware swizzling. texture_format_needs_swiz should return true when the return value of the memcmp is non-zero. Fixes: 751ae6afbefd ("etnaviv: add support for swizzled texture formats") Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marek Vasut <marex@denx.de> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com> (cherry picked from commit 52e93e309f34972dfd5b84075c13ae8d6b9f63df) - radv: Mark GTT memory as device local for APUs. Otherwise a lot of games complain about not having enough memory, and it is sort of local so this seems reasonable to me. CC: 18.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit e1df849c3cfe0c9da7d2f62fc78be94632949903) - travis: radv needs LLVM 4.0 This is a backport for 18.0 from 6ce400782c ("travis: radeonsi and radv need LLVM 4.0") that fixes Travis build with meson + vulkan. CC: 18.0 <mesa-stable@lists.freedesktop.org> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Andres Gomez <agomez@igalia.com> - i965: Fix shadow batches to be the same size as the real BO. brw_bo_alloc may round up our allocation size to the next bucket size. In this case, we would malloc a shadow buffer that was the original intended size, but use bo->size (the larger size) for all of our checks. This could cause us to run off the end of the shadow buffer. v2: Actually use the new BO size (caught by Lionel) Reported-by: James Xiong <james.xiong@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: c7dcee58b5fe183e1653c13bff6a212f0d157b29 (i965: Avoid problems from referencing orphaned BOs after growing.) (cherry picked from commit da25ae92bebb8921003c0df30820d06a5f5e3fef) - radv: fix scissor computation when using half-pixel viewport offset 'scale[i]' can be non-integer. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074 Fixes: 0f3de89a56a ("radv: Use the guard band.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Niuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 893e19efb74edd6133a607e09338bf5d449632f1) - anv: fix number of planes for depth & stencil We're not counting correctly with depth & stencil images. Additionally we need to move an assert that is meant just for color attachments. v2: Move an assert() (Reported by Craig) Change aspect mask checks (Francesco) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: a62a97933578a ("anv: enable multiple planes per image/imageView") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105994 Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (cherry picked from commit 0a6547014fbe5371f5b7253f2c2640ad0026b184) - mesa: free debug messages when destroying the debug state Fixes: 04a8baad3721 "mesa: refactor _mesa_PopDebugGroup and _mesa_free_errors_data" Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98281 (cherry picked from commit a63e69f5f0b4d960bd106068d8c7d13b82fea759) - svga: Fix incorrect advertizing of EGL_KHR_gl_colorspace When advertizing this extension, egl_dri2 uses the DRI2_RENDERER_QUERY extension to query whether an sRGB format is supported. That extension will query our driver with the BIND flag PIPE_BIND_RENDER_TARGET rather than PIPE_BIND_DISPLAY_TARGET which is used when building the configs. We only return the correct value for PIPE_BIND_DISPLAY_TARGET. The inconsistency causes EGL to crash at surface initialization if sRGB is not supported. Fix this by supporting both bind flags. Testing done: piglit egl_gl_colorspace srgb Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> (cherry picked from commit e0c08183fb20399128ff363467e00aa1e8767886) - glsl_to_tgsi: try harder to lower unsupported ir_binop_vector_extract This fixes some piglits. Cc: 18.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit 7bd24d951a69292b5a8090000541ece2142591ef) - radeonsi/gfx9: fix a hang with an empty first IB This packet causes the no-op IB detection to fail, so the IB is always submitted. Also fix the no-op IB detection by moving the begin call. Cc: 18.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> - ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too. No clue how I missed those ... Fixes: 4503ff760c "ac/nir: Add workaround for GFX9 buffer views." CC: <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105320 Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit b0e3a9b19f16ed1ce4c1f150718b0c0f0e6111f6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/common/ac_nir_to_llvm.c - docs: add sha256 checksums for 18.0.1 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: add release notes for 18.0.1 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - Update version to 18.0.1 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - st/va: Enable vaExportSurfaceHandle() It is present from libva 2.1 (VAAPI 1.1.0 or higher). Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Christian König <christian.koenig@amd.com> (cherry picked from commit 768f1487b0c084507ba5e2641e0bbf4ec789ec85) - meson: fix HAVE_LLVM version define in meson build LLVM patch level is not included in HAVE_LLVM. Fixes: e6418ab1566d ("meson: build "radv" vulkan driver for radeon hardware") Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Dylan Baker <dylan.c.baker@intel.com> Signed-off-by: Marc Dietrich <marvin24@gmx.de> (cherry picked from commit a2a1b0e75ef9adeb17468509c5f6331b42f6dc2e) - radv: fix radv_layout_dcc_compressed() when image doesn't have DCC num_dcc_levels means that DCC is supported, but this doesn't mean that it's enabled by the driver. Instead, we should rely on radv_image_has_dcc(). This fixes some multisample regressions since 0babc8e5d66 ("radv: fix picking the method for resolve subpass") on Vega. This is because the resolve method changed from HW to FS, but those fails are totally unexpected, so there might some differences between Polaris and Vega here. Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer dest.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 9eac49246cdc501530418e8bd2a3e6d47173332b) [Juan A. Suarez: do not call radv_image_has_dcc(), as it is not defined] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - radv: fix picking the method for resolve subpass The source and destination image parameters were swapped. No CTS changes on Polaris10, but I suspect this might fix something. Fixes: 2a04f5481df ("radv/meta: select resolve paths") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 0babc8e5d665e54783c926b89183ab9a596aa04c) - radv: Always reset draw user SGPRs after secondary command buffer. As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 41fbcc7901bc7a95fb7d5ccffdb3c18ba0361c40) - radv: Don't set instance count using predication. The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 74b0b869ddd4dbd36482aa9bec3403d45396af2d) - mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage Fixes: 03fd6704db9 ("mesa: Add support for a new override string MESA_GLES_VERSION_OVERRIDE") Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 7cf3932098aba5fefaf241e35ee276b82e6e8ec7) - mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override v2: - Provide a correct explanation on the envvars documentation (Ian). - Provide a more correct explanation on the function comments (Andres). v3: - Homogenize documentation and inline comments (Emil). - Correct a typo (Emil). Fixes: 2599b92eb97 ("mesa: allow forcing >=3.1 compatibility contexts with MESA_GL_VERSION_OVERRIDE") Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ian Romanick <ian.d.romanick@intel.com> Cc: Eric Engestrom <eric.engestrom@imgtec.com> Cc: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 806ab42c0f53064a774f002e311cfbb7ff10a667) - dri_util: when overriding, always reset the core version This way we won't fail when validating just because we may have a non overriden core version that is lower than the requested one, even when the compat version is high enough. For example, running glcts from VK-GL-CTS with i965, this will succeed: $ MESA_GL_VERSION_OVERRIDE=4.6 ./glcts --deqp-case=KHR-GL46.info.vendor While, this will fail: $ MESA_GL_VERSION_OVERRIDE=4.6COMPAT ./glcts --deqp-case=KHR-GL46.info.vendor Fixes: 464c56d3d5c ("dri_util: Use _mesa_override_gl_version_contextless") Cc: Ian Romanick <ian.d.romanick@intel.com> Cc: Tapani Pälli <tapani.palli@intel.com> Cc: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit 044acd3569cbe689712be3c35544ceb7da4e5347) - meson: fix megadriver symlinking Which should be relative instead of absolute. Fixes: f7f1b30f81e842db6057591470ce3cb6d4fb2795 ("meson: extend install_megadrivers script to handle symmlinking") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105567 Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-and-Tested-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 6ac87c17695ebf300a81ecc61e5703c6492b6e5c) - meson: Set .so version for xa like autotools does Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc ("meson: build gallium xa state tracker") Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 19dbed6477525bff2918182b06bf01314f3cd5e9) - nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination Otherwise we may end up trying to coalesce in a case such as ssa_1 = fadd r1, r2 r3.x = fneg(r2); r3 = vec4(ssa_1, ssa_1.y, ...) and that would cause us to move the writes to r3 from the vec to the fadd which would re-order them with respect to the write from the fneg. In order to solve this, we just don't coalesce if the destination of the vec is not SSA. We could try to get clever and still coalesce if there are no writes to the destination of the vec between the vec and the ALU source. However, since registers only come from phi webs and indirects, the chances of having a vec with a register destination that is actually coalescable into its source is very slim. Shader-db results on Haswell: total instructions in shared programs: 13657906 -> 13659101 (<.01%) instructions in affected programs: 149291 -> 150486 (0.80%) helped: 0 HURT: 592 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440 Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible" Reported-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Tested-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 800df942eadc5356840f5cbc2ceaa8a65c01ee91) - glsl: always call do_lower_jumps() after loop unrolling This fixes a bug in radeonsi where LLVM cannot handle the case where a break exists but its not the last instruction in the block. LLVM would fail with: Terminator found in the middle of a basic block! LLVM ERROR: Broken function found, compilation aborted! Fixes: 96fe8834f539 "glsl_to_tgsi: do fewer optimizations with GLSLOptimizeConservatively" Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105317 (cherry picked from commit b42633db8e3711e54a5bd10495b1436b8e362801) - gallium/pipebuffer: fix parenthesis location Without this the return value will never get set to -1. This was first added in 49866c8f3457 and copied in 2b396eeed983. Fixes: 2b396eeed983 "gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager" Reviewed-by: Marek Olšák <marek.olsak@amd.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102342 (cherry picked from commit 7e9b7ec094500f1245eed518592f99244e54a753) - st/dri: Initialise modifier to INVALID for DRI2 When allocating a buffer for DRI2, set the modifier to INVALID to inform the backend that we have no supplied modifiers and it should do its own thing. The missed initialisation forced linear, even if the implementation had made other decisions. This resulted in VC4 DRI2 clients failing with: Modifier 0x0 vs. tiling (0x700000000000001) mismatch Signed-off-by: Daniel Stone <daniels@collabora.com> Reported-by: Andreas Müller <schnitzeltony@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Fixes: 3f8513172ff6 ("gallium/winsys/drm: introduce modifier field to winsys_handle") (cherry picked from commit 4cbecb61682a0ee426faaa03d824fc8fd7aef826) - intel/vec4: Set channel_sizes for MOV_INDIRECT sources Otherwise, any indirect push constant access results in an assertion failure when we start digging through the channel_sizes array. This fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert on Haswell. It should be a harmless no-op for GL since indirect push constants aren't used there. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..." (cherry picked from commit 2b977989f3f01c186677988494bbf9b7342b31f2) - ac/nir: Add workaround for GFX9 buffer views. On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4503ff760c794c3bb15b978a47c530037d56498e) [Juan A. Suarez: partially backported from 908a0cd1dbe5, a backport for 17.3 stable branch; resolved trivial conflicts] Conflicts: src/amd/common/ac_nir_to_llvm.c src/amd/vulkan/radv_nir_to_llvm.c - autotools: include meson_get_version Otherwise meson won't read the VERSION file and won't set a version. That means that pkg-config files will have version unset as well. Fixes: 3e9533d9b88d75d99632fa40e38cfed842d10842 ("meson: Add script to use VERSION file for getting version") Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit bc2fdb9759dc702ec351a044b3fd408c0701fedb) - gbm: remove never-implemented function I assume this was implemented in a previous version of that commit, but was removed in the version that actually landed. Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform" Cc: Giovanni Campagna <gcampagna@src.gnome.org> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 431a1d12cc48060366caf49da76108cd0406b0f6) - nir: fix crash in loop unroll corner case When an if nesting inside anouther if is optimised away we can end up with a loop terminator and following block that looks like this: if ssa_596 { block block_5: /* preds: block_4 */ vec1 32 ssa_601 = load_const (0xffffffff /* -nan */) break /* succs: block_8 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 */ } block block_7: /* preds: block_6 */ vec1 32 ssa_602 = phi block_6: ssa_552 vec1 32 ssa_603 = phi block_6: ssa_553 vec1 32 ssa_604 = iadd ssa_551, ssa_66 The problem is the phis. Loop unrolling expects the last block in the loop to be empty once we splice the instructions in the last block into the continue branch. The problem is we cant move phis so here we lower the phis to regs when preparing the loop for unrolling. As it could be possible to have multiple additional blocks/ifs following the terminator we just convert all phis at the top level of the loop body for simplicity. We also add some comments to loop_prepare_for_unroll() while we are here. Fixes: 51daccb289eb "nir: add a loop unrolling pass" Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670 (cherry picked from commit 629ee690addad9b3dc8f68cfff5ae09858f31caf) - glsl: fix infinite loop caused by bug in loop unrolling pass Just checking for 2 jumps is not enough to be sure we can do a complex loop unroll. We need to make sure we also have also found 2 loop terminators. Without this we were attempting to unroll a loop where the second jump was nested inside multiple ifs which loop analysis is unable to detect as a terminator. We ended up splicing out the first terminator but failed to actually unroll the loop, this resulted in the creation of a possible infinite loop. Fixes: 646621c66da9 "glsl: make loop unrolling more like the nir unrolling path" Tested-by: Gert Wollny <gw.fossdev@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670 (cherry picked from commit 56b867395dee1a48594b27987d3bf68a4e745dda) Squashed with: glsl: remove unreachable assert() Earlier commit enforced that we'll bail out if the number of terminators is different than 2. With that in mind, the assert() will never trigger. Fixes: 56b867395de ("glsl: fix infinite loop caused by bug in loop unrolling pass") Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 8eceac9de7d3cd4fddabbe61d512acfed9812169) - i965/perf: fix config registration when uploading to kernel When registring configurations to the kernel for the first time, we run into an issue where the id number is not properly set (we're using the wrong variable). As a result when trying to use that id later on, we get an error. This issue manifest itself the first time you use frameretrace after reboot, subsequent runs are fine. Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations") Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 1603ce1921a511f128025a49d055283440376231) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/brw_performance_query.c - cherry-ignore: omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA} fixes: The commit fixes earlier commits 83d4a5d5aea5a8a05be2, b2f2236dc565dd1460f0 and c62cf1f165919bc74296 which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - anv/pipeline: fail if TCS/TES compile fail v2: Add Fixes tag. (Lionel) Fixes: e50d4807a35e679 ("anv: Compile TCS/TES shaders.") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 318073ce660ca72b47ba83e37d1d0bc756f779b7) - cherry-ignore: radv: handle exporting view index to fragment shader. (v1.1) fixes: The commit requieres earlier commits 639c4f2b54a6 and 2cfba40eea4c which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - cherry-ignore: ac/shader: fix vertex input with components. fixes: The commit fixes earlier commit 1c57a6da5e3 which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - ac: make use of if/loop build helpers These helpers insert the basic block in the same order as they appear in NIR making it easier to follow LLVM IR dumps. The helpers also insert more useful labels onto the blocks. TGSI use the line number of the corresponding opcode in the TGSI dump as the label id, here we use the corresponding block index from NIR. Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 99cdc019bf6fe11c135b7544ef6daf4ac964fa24) - radeonsi: make use of if/loop build helpers in ac Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 6e1a142863b368a032e333f09feb107241446053) - ac: add if/loop build helpers These have been ported over from radeonsi. Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 42627dabb4db3011825a022325be7ae9b51103d6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/common/ac_llvm_build.c src/amd/common/ac_llvm_build.h - meson: don't use compiler.has_header Meson's compiler.has_header is completely useless, it only checks that a header exists, not whether it's usable. This creates problems if a header contains a conditional #error declaration, like so: > #if __x86_64__ > # error "Doesn't work with x86_64!" > #endif Compiler.has_header will return true in this case, even when compiling for x86_64. This is useless. Instead, we'll do a compile check so that any #error declarations will be treated as errors, and compilation will work. Fixes compilation on x32 architecture. Gentoo Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=649746 meson bug: https://github.com/mesonbuild/meson/issues/2246 Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Acked-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit 8247a30838a74dcdd27cc2468bff8a3d8def640e) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: meson.build - egl/wayland: Make swrast display_sync the correct queue commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface queues, but the display_sync for swrast_commit_backbuffer remained on the old queue. This is likely to break when dispatching the correct queue at the top of function (which can't dispatch the sync callback we're waiting for). The easiest known reproduction case is running weston-subsurfaces under weston --use-pixman Signed-off-by: Derek Foreman <derekf@osg.samsung.com> Reviewed-by: Daniel Stone <daniels@collabora.com> (cherry picked from commit aa18a63512ccfa4eb8bc5d043e8967738a465af4) - i965: return the fourcc saved in __DRIimage when possible When creating a image from a texture, the image's dri_format is set to the first plane's format, and used to look up for the fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to __DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function intel_lookup_fourcc(): { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, instead of the correct one: { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned. To fix this bug, the image inherits the texture's planar_format that has the original fourcc; Upon querying, if planar_format is set, return the saved fourcc; Otherwise fall back to the old way. v3: add a bug description and "cc mesa-stable" tag (Jason) remove redundant null pointer check (Tapani) squash 2 patches into one (James) v2: fall back to intel_lookup_fourcc() when planar_format is NULL (Dongwon & Matt Roper) Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Xiong, James <james.xiong@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit f23b45dce3888112b7d26a623ab1280ce86533a1) - st/nine: Do not use scratch for face register Scratch registers are reused every instructions. Since vFace is reused, a new temporary register should be used. Fixes: https://github.com/iXit/Mesa-3D/issues/311 Signed-off-by: Axel Davy <davyaxel0@gmail.com> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit d899826733b1f6614c913c1c216f8157bf9e297d) - st/nine: Declare lighting consts for ff shaders The lighting constants were not declared previously, but were accessed with indirect addressing, which is illegal. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105442 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 39240926cd45519f35a6fa576c387f727b057aa1) - compiler/spirv: set is_shadow for depth comparitor sampling opcodes From the SPIR-V spec, OpTypeImage: "Depth is whether or not this image is a depth image. (Note that whether or not depth comparisons are actually done is a property of the sampling opcode, not of this type declaration.)" The sampling opcodes that specify depth comparisons are OpImageSample{Proj}Dref{Explicit,Implicit}Lod, so we should set is_shadow only for these (we were using the deph property of the image until now). v2: - Do the same for OpImageDrefGather. - Set is_shadow to false if the sampling opcode is not one of these (Jason) - Reuse an existing switch statement instead of adding a new one (Jason) Fixes crashes in: dEQP-VK.spirv_assembly.instruction.graphics.image_sampler.depth_property.* Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 41ac0b1443ca7c8c3481eab978a41b7caba5503a) - i965: Extend the negative 32-bit deltas to 64-bits Gen8+ use 48-bit address relocations so need to extend the sign to 64-bit return value. Without it we have higher bits zeroed and missing the negavive values. Haswell and older use 32-bit deltas so are unaffected by this issue. v2: used int32_t fucntion parameter instead of explicit type conversion. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101408 Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Tested-by: Andriy Khulap <andriy.khulap@globallogic.com> Tested-by: Stuart Young <cefiar@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "18.0 17.3" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 98b860e3115ff937152dbf4c843e1ecb9244734c) - freedreno/a5xx: don't align height for PIPE_BUFFER Buffers can be large, so we probably don't want to make them all 32x bigger. But they can't be rendered to (at least in GL) so we don't need this workaround to prevent page faults on mem<->gmem. Cc: "18.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 2f175bfe5d8ca59a8a68b6d6d072cd7bf2f8baa9) - freedreno/a5xx: fix page faults on last level We could alternatively fall back to using "old style" draw's for mem<->gmem (ie. what <= a4xx do) when height is not aligned to 32, but that is somewhat more work (and not really something that could be applied to stable) Cc: "18.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Rob Clark <robdclark@gmail.com> (cherry picked from commit 1866f76f7bc3ec54b4e91eb7d329b2e6f7b6277c) - nir/lower_indirect_derefs: Support interp_var_at intrinsics This fixes the fs-interpolateAtCentroid-block-array piglit test on i965. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 6018f5b07966a0f85dea1ee6775d50a8c85fdee1) - nir/vars_to_ssa: Remove copies from the correct set Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 0517d65f9639349d626aeb2af48ba9e4e605900d) - mesa: Inherit texture view multi-sample information from the original texture images. Found running "The Witness" in Wine. Without this patch, texture views created on multi-sample textures would have a GL_TEXTURE_SAMPLES of 0. All things considered such views actually work surprisingly well, but when combined with (plain) multi-sample textures in a framebuffer object, the resulting FBO is incomplete because the sample counts don't match. CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Henri Verbeet <hverbeet@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com> (cherry picked from commit 0b73c86b8030a7f7cb35fc85c83eff7f2b8c24a4) - docs: fix 18.0 release note version Fixes: 839fb3a696679bfe975c2 "docs: Update 18.0.0 release notes" Cc: "18.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit d77844a5290948a490ce6921c1623d1dd7af6c31) - nir: fix per_vertex_output intrinsic This is supposed to have both BASE and COMPONENT but num_indices was inadvertantly set to 1. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit cc3a88e81dbceb12b79eb4ebe7a4ce5ba97fc291) - i965/vec4: Fix null destination register in 3-source instructions A recent commit (see below) triggered some cases where conditional modifier propagation and dead code elimination would cause a MAD instruction like the following to be generated: mad.l.f0 null, ... Matt pointed out that fs_visitor::fixup_3src_null_dest() fixes cases like this in the scalar backend. This commit basically ports that code to the vec4 backend. NOTE: I have sent a couple tests to the piglit list that reproduce this bug *without* the commit mentioned below. This commit fixes those tests. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Tapani Pälli <tapani.palli@intel.com> Cc: mesa-stable@lists.freedesktop.org Fixes: ee63933a7 ("nir: Distribute binary operations with constants into bcsel") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105704 (cherry picked from commit 91225cb33f0baede872114bd416084b3b52937a1) - meson/configure: detect endian.h instead of trying to guess when it's available Cc: Maxin B. John <maxin.john@gmail.com> Cc: Khem Raj <raj.khem@gmail.com> Cc: Rob Herring <robh@kernel.org> Suggested-by: Jon Turney <jon.turney@dronecode.org.uk> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Cc: <mesa-stable@lists.freedesktop.org> (cherry picked from commit cbee1bfb34274668a05995b9d4c78ddec9e5ea4c) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: meson.build Squashed with: configure: use AC_CHECK_HEADERS to check for endian.h The currently we use the singular CHECK_HEADER combined with explicit append to the DEFINES variable. That is a legacy misnomer, since it requires us to add $DEFINES to every piece that we build. Using the plural version of the helper sets the HAVE_ macro for us, plus ensures it's passed to the compiler - if config.h is available in there (not in the case of mesa) otherwise on the command line. In hindsight, we should replace all the AC_CHECK_{FUNC,HEADER} instances with the plural version (or even the _ONCE suffixed version) and drop the DEFINES hacks. Fixes: cbee1bfb342 ("meson/configure: detect endian.h instead of trying to guess when it's available") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105717 Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Eric Engestrom <eric.engestrom@imgtec.com> Tested-by: Clayton Craft <clayton.a.craft@intel.com> (cherry picked from commit 5a75019ad0270a974788a9b8648ba98ff4203768) - radeon/vce: move feedback command inside of destroy function On the CI family, firmware requires the destory command have to be the last command in the IB, moving feedback command after destroy is causing issues on CI cards, so we have to keep the previous logic that moves destroy back to the last command. But as the original issue fixed previously, with the newer family like Vega10, feedback command have to be included inside of the task info command along with destroy command. Fixes: 6d74cb25("radeon/vce: move destroy command before feedback command") Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit c4de2f0880cfa49bd6fd3138564ee64ef4e637a1) - st/nine: Fix non inversible matrix check There was a missing absolute value when checking if the determinant was big enough. Fixes: https://github.com/iXit/Mesa-3D/issues/292 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit dbc24835d75466951a44b391b42e39461a6ac5a2) - st/nine: Fixes warning about implicit conversion Makes the conversion explicit. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102542 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit f61e9a958bd8d61cb7ca575ca987caefc6edbffd) - st/nine: Fix bad tracking of vs textures for NINESBT_ALL Stateblocks with NINESBT_ALL should track all textures. For better performance they have a faster path which copies all the required. This path was only tracking ps textures. Fixes: https://github.com/iXit/Mesa-3D/issues/303 Signed-off-by: Axel Davy <davyaxel0@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 71eae7940ef7fa92e01cdc9afa1172f92d4b489e) - cherry-ignore anv: Be more careful about fast-clear colors stable: There is a specific version for this patch for stable branches, but it is causing regressions. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> - docs: add sha256 checksums for 18.0.0 Signed-off-by: Emil Velikov <emil.velikov@collabora.com> - docs: Update 18.0.0 release notes Note: the file was originally 17.4.0, yet git stuggles to detect the move :-\ Signed-off-by: Emil Velikov <emil.velikov@collabora.com> - Update version to 18.0.0(final) Signed-off-by: Emil Velikov <emil.velikov@collabora.com> - Update version to 18.0.0-rc5 Signed-off-by: Emil Velikov <emil.velikov@collabora.com> - radeonsi: prevent a negative buffer offset in si_upload_descriptors (cherry picked from commit 16856a1ee86f364212674dddf154caa374310a6b) - radeonsi: fix vertex buffer address computation with full 64-bit addresses (cherry picked from commit 2a47660754ba49d5998929550f639677506c4515) - travis: keep meson version below 0.45.0 Recently Meson upgraded to 0.45.0 and it needs python 3.5+, which is not available in Trusty. Cc: Eric Engestrom <eric.engestrom@imgtec.com> Cc: Dylan Baker <dylan@pnwbakers.com> Cc: Emil Velikov <emil.velikov@collabora.com> Cc: Jon Turney <jon.turney@dronecode.org.uk> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (cherry picked from commit 72552012c7b461b887c44b3f90e2744bc7512a74) - travis: make Meson find the proper llvm-config Travis CI has moved to LLVM 5.0, and meson is detecting automatically the available version in /usr/local/bin based on the PATH env variable order preference. As for 0.44.x, Meson cannot receive the path to the llvm-config binary as a configuration parameter. See https://github.com/mesonbuild/meson/issues/2887 and https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef We want to use the custom (APT) installed version. Therefore, let's make Meson find our wanted version sooner than the one at /usr/local/bin Once this is corrected, we would still need a patch similar to: https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html v2: Create the link only to the specificly wanted LLVM version (Gert). Cc: Eric Engestrom <eric.engestrom@imgtec.com> Cc: Dylan Baker <dylan@pnwbakers.com> Cc: Emil Velikov <emil.velikov@collabora.com> Cc: Juan A. Suarez Romero <jasuarez@igalia.com> Cc: Gert Wollny <gw.fossdev@gmail.com> Cc: Jon Turney <jon.turney@dronecode.org.uk> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-and-Tested-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> Reviewed-By: Gert Wollny <gw.fossdev@gmail.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit b5b912dfeebabafbaff176fe4205eb74607f709b) - mesa: add glsl version query (v4) Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS and glGetStringi for GL_SHADING_LANGUAGE_VERSION v2: - Combine similar functionality into _mesa_get_shading_language_version() function. - Change GLSL version return mechanism. v3: - Add return of empty string for GLSL ver 1.10. - Move _mesa_get_shading_language_version() function to src/mesa/main/version.c. v4: - Add OpenGL version check. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915 Signed-off-by: Andriy Khulap <andriy.khulap@globallogic.com> Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Reviewed-by: Brian Paul <brianp@vmware.com> (cherry picked from commit a553c54abf92533daf442073dd3408c35f57d8ba) - i965: Silence compiler warning about promoted_constants. We only have a cfg != NULL if we went through one of the paths that set it, but my compiler doesn't figure that out. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 6411defdcd6f ("intel/cs: Re-run final NIR optimizations for each SIMD size") (cherry picked from commit d25640c3a3b914059abd661f0651d88b4fe408e8) - radv: mark all tess output for an indirect access. If a shader does a tcs store with an indirect access, we were only marking the first spot as used. For indirect access we always now mark all slots used by the variable. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 27a5e5366e89498d98d786cc84fafbdb220c4d94) Emil Velikov: move hunks {radv,ac}_nir_to_llvm.c] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/vulkan/radv_nir_to_llvm.c - ac/nir: pass the nir variable through tcs loading. I was going to have to add another parameter to this monster, so we should just pass the nir_variable in, I can't find any reason this would be a bad idea. This needed for the next fix. Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 4f0c89d66c570e82d832e2e49227517302e271a2) [Emil Velikov: move hunk {radv,ac}_nir_to_llvm.c] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/common/ac_nir_to_llvm.c src/amd/common/ac_shader_abi.h src/amd/vulkan/radv_nir_to_llvm.c - radv: get correct offset into LDS for indexed vars. This seems more correct to me, since if we have an array of floats they'll be vec4 aligned, and if we do af[2], we want the const index to increase by 2 slots in the non compact case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit f9de2d409bf4f068a99d358d592d96ab4803f7fb) [Emil Velikov: hunk belongs to another file {radv,ac}_nir_to_llvm.c] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/vulkan/radv_nir_to_llvm.c - i965: Emit texture cache invalidates around blorp_copy This is a terrible hack but it fixes CTS regressions. It's still incredibly unclear exactly what is going wrong in the hardware to cause this to be an issue so this isn't a good fix by any means. However, it does fix tests so there is that. Fixes: fb0e9b5197 "i965: Track the depth and render caches separately" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103746 Acked-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 8379bff6c4456f8a77041eee225dcd44e5e00a76) - meson: Add moduledir to d3d.pc This is required to build wine with the nine patchset Fixes: 6b4c7047d57178d3362a710ad503057c6a582ca3 ("meson: build gallium nine state_tracker") Reported-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit b7c6870f87acafd592629d1c3127b54e52689f02) - mesa: Don't write to user buffer in glGetTexParameterIuiv on error With some sets of optimization flags, GCC will generate warnings like this: src/mesa/main/texparam.c:2327:27: warning: ‘*((void *)&ip+12)’ may be used uninitialized in this function [-Wmaybe-uninitialized] params[3] = ip[3]; ~~^~~ src/mesa/main/texparam.c:2320:16: note: ‘*((void *)&ip+12)’ was declared here GLint ip[4]; ^~ ip is not initialized in cases where a GL error is generated. In these cases, we should *not* write to the user's buffer, so this is actually a bug. I wrote a new piglit test gl-3.0-texparameteri to show this bug. I suspect that Coverity also detected this, but the scan site is currently down. Fixes: c2c507786 "main: Added entry points for glGetTextureParameteriv, Iiv, and Iuiv." Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit def0030e64dd3a4eb3487dd40bf64b9a71a70af3) - st/dri: fix OpenGL-OpenCL interop for GL_TEXTURE_BUFFER Tested by our OpenCL team. Fixes: 9c499e6759b26c5e "st/mesa: don't invoke st_finalize_texture & st_convert_sampler for TBOs" Acked-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit db495b8962909f74e90b9eb0463fb37f37ac5f62) - autotools: include all meson.build files Otherwise SWR cannot be built with meson from an autotools generated tarball, such as the 18.0.0-rc4 tarball. Fixes: 16bf81383080 ("meson/swr: re-shuffle generated files") Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: George Kyriazis <george.kyriazis@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit 7258be91c59b20a6479b3b0d750ff8b4a32cf032) - radv: Fix copying from 3D images starting at non-zero depth. Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit eea20d59abd304953c8c1591612d45d3d94eb785) - swr/rast: Fix macOS macro. Fixes: a25093de7188 ("swr/rast: Implement JIT shader caching to disk") Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-By: George Kyriazis <george.kyriazis@intel.com> (cherry picked from commit bb742b6ebf2d8c8dcc77f69b44995be2971e116a) - meson: install vulkan_intel.h header Fixes: d1992255bb29054fa51763376d125183a9f602f3 ("meson: Add build Intel "anv" vulkan driver") Signed-off-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit e23192022a2cde122a6ccc70e5495fda009bee12) - i965: Fix RELOC_WRITE typo in brw_store_data_imm64() Fixes: 6c530ad11605 ("i965: Reduce passing 2x32b of reloc_domains to 2 bits") Signed-off-by: Andriy Khulap <andriy.khulap@globallogic.com> Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 7859701920adc7f25696a05ae4715a4694109e1d) - i965/sbe: fix number of inputs for active components In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry. Unfortunately, there are some special inputs that are not stored in the URB and that we also need to account for. These special inputs are identified and handled during calculate_attr_overrides(). Ins…

siro20 added the bug label Jan 29, 2018

siro20 assigned siro20 and axeldavy Jan 29, 2018

axeldavy closed this as completed Mar 10, 2018

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[nine][shader] Guild Wars 2 with Shaders on "medium" #303

[nine][shader] Guild Wars 2 with Shaders on "medium" #303

siro20 commented Jan 29, 2018

siro20 commented Feb 25, 2018

axeldavy commented Mar 4, 2018

siro20 commented Mar 6, 2018

axeldavy commented Mar 10, 2018

[nine][shader] Guild Wars 2 with Shaders on "medium" #303

[nine][shader] Guild Wars 2 with Shaders on "medium" #303

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siro20 commented Jan 29, 2018

siro20 commented Feb 25, 2018

axeldavy commented Mar 4, 2018

siro20 commented Mar 6, 2018

axeldavy commented Mar 10, 2018