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update main (#14)
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* Update README.md

* update 20230706

Confirmed DT1 logic: no problem
Switch to blocking assignments in always@(*) block
Update readme
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@ika-musume
ika-musume committed Jul 6, 2023
1 parent 7cea2df commit a49d79d
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46 changes: 23 additions & 23 deletions HDL/IKAOPM_modules/IKAOPM_eg.v
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Expand Up @@ -337,10 +337,10 @@ always @(*) begin
end
else begin
case(cyc6r_cyc9r_envstate_previous[1])
ATTACK: cyc8c_egparam <= i_AR;
FIRST_DECAY: cyc8c_egparam <= i_D1R;
SECOND_DECAY: cyc8c_egparam <= i_D2R;
RELEASE: cyc8c_egparam <= {i_RR, 1'b0};
ATTACK: cyc8c_egparam = i_AR;
FIRST_DECAY: cyc8c_egparam = i_D1R;
SECOND_DECAY: cyc8c_egparam = i_D2R;
RELEASE: cyc8c_egparam = {i_RR, 1'b0};
endcase
end
end
Expand Down Expand Up @@ -496,25 +496,25 @@ end
reg cyc10c_envdeltaweight_intensity; //0 = weak, 1 = strong
always @(*) begin
case({cyc9r_egparam_scaled[1:0], cyc9r_envcntr})
4'b00_00: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b00_01: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b00_10: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b00_11: cyc10c_envdeltaweight_intensity <= 1'b0;

4'b01_00: cyc10c_envdeltaweight_intensity <= 1'b1;
4'b01_01: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b01_10: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b01_11: cyc10c_envdeltaweight_intensity <= 1'b0;

4'b10_00: cyc10c_envdeltaweight_intensity <= 1'b1;
4'b10_01: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b10_10: cyc10c_envdeltaweight_intensity <= 1'b1;
4'b10_11: cyc10c_envdeltaweight_intensity <= 1'b0;

4'b11_00: cyc10c_envdeltaweight_intensity <= 1'b1;
4'b11_01: cyc10c_envdeltaweight_intensity <= 1'b1;
4'b11_10: cyc10c_envdeltaweight_intensity <= 1'b1;
4'b11_11: cyc10c_envdeltaweight_intensity <= 1'b0;
4'b00_00: cyc10c_envdeltaweight_intensity = 1'b0;
4'b00_01: cyc10c_envdeltaweight_intensity = 1'b0;
4'b00_10: cyc10c_envdeltaweight_intensity = 1'b0;
4'b00_11: cyc10c_envdeltaweight_intensity = 1'b0;

4'b01_00: cyc10c_envdeltaweight_intensity = 1'b1;
4'b01_01: cyc10c_envdeltaweight_intensity = 1'b0;
4'b01_10: cyc10c_envdeltaweight_intensity = 1'b0;
4'b01_11: cyc10c_envdeltaweight_intensity = 1'b0;

4'b10_00: cyc10c_envdeltaweight_intensity = 1'b1;
4'b10_01: cyc10c_envdeltaweight_intensity = 1'b0;
4'b10_10: cyc10c_envdeltaweight_intensity = 1'b1;
4'b10_11: cyc10c_envdeltaweight_intensity = 1'b0;

4'b11_00: cyc10c_envdeltaweight_intensity = 1'b1;
4'b11_01: cyc10c_envdeltaweight_intensity = 1'b1;
4'b11_10: cyc10c_envdeltaweight_intensity = 1'b1;
4'b11_11: cyc10c_envdeltaweight_intensity = 1'b0;
endcase
end

Expand Down
24 changes: 12 additions & 12 deletions HDL/IKAOPM_modules/IKAOPM_lfo.v
View file
Expand Up @@ -387,10 +387,10 @@ reg base_value_input;
always @(*) begin
if(i_CYCLE_BYTE) begin
case(wfsel)
2'd3: base_value_input <= noise_value_stream;
2'd2: base_value_input <= tri_value_stream; //gawr gura
2'd1: base_value_input <= sq_value_stream;
2'd0: base_value_input <= saw_value_stream;
2'd3: base_value_input = noise_value_stream;
2'd2: base_value_input = tri_value_stream; //gawr gura
2'd1: base_value_input = sq_value_stream;
2'd0: base_value_input = saw_value_stream;
endcase
end
else base_value_input <= 1'b0;
Expand Down Expand Up @@ -468,14 +468,14 @@ end
reg multiplier_fa_b;
always @(*) begin
case(multiplier_bitsel)
3'b000: multiplier_fa_b <= base_value_sr[0] & ap_muxed[6];
3'b001: multiplier_fa_b <= base_value_sr[1] & ap_muxed[5];
3'b010: multiplier_fa_b <= base_value_sr[2] & ap_muxed[4];
3'b011: multiplier_fa_b <= base_value_sr[3] & ap_muxed[3];
3'b100: multiplier_fa_b <= base_value_sr[4] & ap_muxed[2];
3'b101: multiplier_fa_b <= base_value_sr[5] & ap_muxed[1];
3'b110: multiplier_fa_b <= base_value_sr[6] & ap_muxed[0];
3'b111: multiplier_fa_b <= 1'b0;
3'b000: multiplier_fa_b = base_value_sr[0] & ap_muxed[6];
3'b001: multiplier_fa_b = base_value_sr[1] & ap_muxed[5];
3'b010: multiplier_fa_b = base_value_sr[2] & ap_muxed[4];
3'b011: multiplier_fa_b = base_value_sr[3] & ap_muxed[3];
3'b100: multiplier_fa_b = base_value_sr[4] & ap_muxed[2];
3'b101: multiplier_fa_b = base_value_sr[5] & ap_muxed[1];
3'b110: multiplier_fa_b = base_value_sr[6] & ap_muxed[0];
3'b111: multiplier_fa_b = 1'b0;
endcase
end

Expand Down
64 changes: 32 additions & 32 deletions HDL/IKAOPM_modules/IKAOPM_op.v
View file
Expand Up @@ -115,19 +115,19 @@ wire odd = cyc42r_logsinrom_phase_odd; //alias signal
reg [10:0] cyc43c_logsinrom_addend0, cyc43c_logsinrom_addend1;
always @(*) begin
case(cyc42r_logsinrom_bitsel)
/* D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc43c_logsinrom_addend0 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[29], ls[25], ls[18], ls[14], ls[3]};
2'd1: cyc43c_logsinrom_addend0 <= { 1'b0, 1'b0, 1'b0, 1'b0, ls[37], ls[34], ls[28], ls[24], ls[17], ls[13], ls[2]};
2'd2: cyc43c_logsinrom_addend0 <= { 1'b0, 1'b0, ls[43], ls[41], ls[36], ls[33], ls[27], ls[23], ls[16], ls[12], ls[1]};
2'd3: cyc43c_logsinrom_addend0 <= {ls[45], ls[44], ls[42], ls[40], ls[35], ls[32], ls[26], ls[22], ls[15], ls[11], ls[0]};
/* D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc43c_logsinrom_addend0 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[29], ls[25], ls[18], ls[14], ls[3]};
2'd1: cyc43c_logsinrom_addend0 = { 1'b0, 1'b0, 1'b0, 1'b0, ls[37], ls[34], ls[28], ls[24], ls[17], ls[13], ls[2]};
2'd2: cyc43c_logsinrom_addend0 = { 1'b0, 1'b0, ls[43], ls[41], ls[36], ls[33], ls[27], ls[23], ls[16], ls[12], ls[1]};
2'd3: cyc43c_logsinrom_addend0 = {ls[45], ls[44], ls[42], ls[40], ls[35], ls[32], ls[26], ls[22], ls[15], ls[11], ls[0]};
endcase

case(cyc42r_logsinrom_bitsel)
/* D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc43c_logsinrom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[7]} & {2'b00, {9{odd}}};
2'd1: cyc43c_logsinrom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[10], ls[6]} & {2'b00, {9{odd}}};
2'd2: cyc43c_logsinrom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[20], ls[9], ls[5]} & {2'b00, {9{odd}}};
2'd3: cyc43c_logsinrom_addend1 <= { 1'b0, 1'b0, ls[39], ls[39], ls[38], ls[31], ls[30], ls[21], ls[19], ls[8], ls[4]} & {2'b00, {9{odd}}};
/* D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[7]} & {2'b00, {9{odd}}};
2'd1: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[10], ls[6]} & {2'b00, {9{odd}}};
2'd2: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ls[20], ls[9], ls[5]} & {2'b00, {9{odd}}};
2'd3: cyc43c_logsinrom_addend1 = { 1'b0, 1'b0, ls[39], ls[39], ls[38], ls[31], ls[30], ls[21], ls[19], ls[8], ls[4]} & {2'b00, {9{odd}}};
endcase
end

Expand Down Expand Up @@ -219,19 +219,19 @@ wire even = cyc46r_logsin_even; //alias signal
reg [9:0] cyc47c_exprom_addend0, cyc47c_exprom_addend1;
always @(*) begin
case(cyc46r_exprom_bitsel)
/* D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc47c_exprom_addend0 <= { 1'b1, e[43], e[40], e[36], e[32], e[28], e[24], e[18], e[14], e[3]};
2'd1: cyc47c_exprom_addend0 <= { e[44], e[42], e[39], e[35], e[31], e[27], e[23], e[17], e[13], e[2]};
2'd2: cyc47c_exprom_addend0 <= { 1'b0, e[41], e[38], e[34], e[30], e[26], e[22], e[16], e[12], e[1]};
2'd3: cyc47c_exprom_addend0 <= { 1'b0, 1'b0, e[37], e[33], e[29], e[25], e[21], e[15], e[11], e[0]};
/* D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc47c_exprom_addend0 = { 1'b1, e[43], e[40], e[36], e[32], e[28], e[24], e[18], e[14], e[3]};
2'd1: cyc47c_exprom_addend0 = { e[44], e[42], e[39], e[35], e[31], e[27], e[23], e[17], e[13], e[2]};
2'd2: cyc47c_exprom_addend0 = { 1'b0, e[41], e[38], e[34], e[30], e[26], e[22], e[16], e[12], e[1]};
2'd3: cyc47c_exprom_addend0 = { 1'b0, 1'b0, e[37], e[33], e[29], e[25], e[21], e[15], e[11], e[0]};
endcase

case(cyc46r_exprom_bitsel)
/* D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc47c_exprom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, e[10], e[7]} & {7'b0000000, {3{even}}};
2'd1: cyc47c_exprom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, e[6]} & {7'b0000000, {3{even}}};
2'd2: cyc47c_exprom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, e[19], e[9], e[5]} & {7'b0000000, {3{even}}};
2'd3: cyc47c_exprom_addend1 <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, e[20], e[8], e[4]} & {7'b0000000, {3{even}}};
/* D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 */
2'd0: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, e[10], e[7]} & {7'b0000000, {3{even}}};
2'd1: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, e[6]} & {7'b0000000, {3{even}}};
2'd2: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, e[19], e[9], e[5]} & {7'b0000000, {3{even}}};
2'd3: cyc47c_exprom_addend1 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, e[20], e[8], e[4]} & {7'b0000000, {3{even}}};
endcase
end

Expand Down Expand Up @@ -264,17 +264,17 @@ end
reg [12:0] cyc48c_shifter0, cyc48c_shifter1;
always @(*) begin
case(cyc47r_level_fp_exp[1:0])
2'b00: cyc48c_shifter0 <= {3'b000, 1'b1, cyc47r_level_fp_mant[9:1]};
2'b01: cyc48c_shifter0 <= {2'b00, 1'b1, cyc47r_level_fp_mant };
2'b10: cyc48c_shifter0 <= {1'b0, 1'b1, cyc47r_level_fp_mant, 1'b0 };
2'b11: cyc48c_shifter0 <= { 1'b1, cyc47r_level_fp_mant, 2'b00 };
2'b00: cyc48c_shifter0 = {3'b000, 1'b1, cyc47r_level_fp_mant[9:1]};
2'b01: cyc48c_shifter0 = {2'b00, 1'b1, cyc47r_level_fp_mant };
2'b10: cyc48c_shifter0 = {1'b0, 1'b1, cyc47r_level_fp_mant, 1'b0 };
2'b11: cyc48c_shifter0 = { 1'b1, cyc47r_level_fp_mant, 2'b00 };
endcase

case(cyc47r_level_fp_exp[3:2])
2'b00: cyc48c_shifter1 <= {12'b0, cyc48c_shifter0[12] };
2'b01: cyc48c_shifter1 <= { 8'b0, cyc48c_shifter0[12:8]};
2'b10: cyc48c_shifter1 <= { 4'b0, cyc48c_shifter0[12:4]};
2'b11: cyc48c_shifter1 <= cyc48c_shifter0;
2'b00: cyc48c_shifter1 = {12'b0, cyc48c_shifter0[12] };
2'b01: cyc48c_shifter1 = { 8'b0, cyc48c_shifter0[12:8]};
2'b10: cyc48c_shifter1 = { 4'b0, cyc48c_shifter0[12:4]};
2'b11: cyc48c_shifter1 = cyc48c_shifter0;
endcase
end

Expand Down Expand Up @@ -372,10 +372,10 @@ reg cyc53c_accumulation_en;
assign o_ACC_SNDADD = cyc53c_accumulation_en;
always @(*) begin
case(cyc52r_algst)
2'd0: cyc53c_accumulation_en <= cyc52r_algtype == 3'd7; //Add M1?
2'd1: cyc53c_accumulation_en <= cyc52r_algtype == 3'd7 || cyc52r_algtype == 3'd6 || cyc52r_algtype == 3'd5; //Add M2?
2'd2: cyc53c_accumulation_en <= cyc52r_algtype == 3'd7 || cyc52r_algtype == 3'd6 || cyc52r_algtype == 3'd5 || cyc52r_algtype == 3'd4; //Add C1?
2'd3: cyc53c_accumulation_en <= 1'b1; //Add C2?
2'd0: cyc53c_accumulation_en = cyc52r_algtype == 3'd7; //Add M1?
2'd1: cyc53c_accumulation_en = cyc52r_algtype == 3'd7 || cyc52r_algtype == 3'd6 || cyc52r_algtype == 3'd5; //Add M2?
2'd2: cyc53c_accumulation_en = cyc52r_algtype == 3'd7 || cyc52r_algtype == 3'd6 || cyc52r_algtype == 3'd5 || cyc52r_algtype == 3'd4; //Add C1?
2'd3: cyc53c_accumulation_en = 1'b1; //Add C2?
endcase
end

Expand Down

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