Add synchronizers on all input lines for godil6502 target

Synchronize the input signals to avoid metastability issues that cause
incorrect data bus reads in a 1541 within a few milliseconds after reset.

targets/godil_6502/godil.v

@@ -19,13 +19,23 @@ module godil40_xc3s500e(
   output [1:0] led
 );
 
+// synchronized signals
+   reg [7:0]  syn_db;
+   reg        syn_res;
+   reg        syn_so;
+   reg        syn_clk0;
+   reg        syn_rdy;
+   reg        syn_nmi;
+   reg        syn_irq;
+
+
 // handle three-state data bus
 
   wire [7:0] db_i;
   wire [7:0] db_o;
   wire [7:0] db_t;  // not yet properly set by the 6502 model; instead use rw for the three-state enable for all db pins
 
-  assign db_i = db;
+  assign db_i = syn_db;
   assign db = rw ? 8'bz : db_o;
 
 // create an emulation clock from clk_49152mhz
@@ -34,6 +44,17 @@ module godil40_xc3s500e(
 
   clock_and_reset _clk(clk_49152mhz, eclk, ereset);
 
+// synchronize external input signals
+   always @(posedge eclk) begin
+      syn_db   = db;
+      syn_res  = res;
+      syn_so   = so;
+      syn_clk0 = clk0;
+      syn_rdy  = rdy;
+      syn_nmi  = nmi;
+      syn_irq  = irq;
+   end
+
 // blink an LED using eclk
 
   blink #(26) _blink0(eclk, led[0]);
@@ -46,7 +67,7 @@ module godil40_xc3s500e(
     ab[0], ab[1], ab[2], ab[3], ab[4], ab[5], ab[6], ab[7], ab[8], ab[9], ab[10], ab[11], ab[12], ab[13], ab[14], ab[15],
     db_i[0], db_o[0], db_t[0], db_i[1], db_o[1], db_t[1], db_i[2], db_o[2], db_t[2], db_i[3], db_o[3], db_t[3], 
     db_i[4], db_o[4], db_t[4], db_i[5], db_o[5], db_t[5], db_i[6], db_o[6], db_t[6], db_i[7], db_o[7], db_t[7], 
-    res, rw, sync, so, clk0, clk1out, clk2out, rdy, nmi, irq);
+    syn_res, rw, sync, syn_so, syn_clk0, clk1out, clk2out, syn_rdy, syn_nmi, syn_irq);
 
 endmodule