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Added Digiteq Automotive MGB4 driver
Digiteq Automotive MGB4 is a modular frame grabber PCIe card for automotive video interfaces. As for now, two modules - FPD-Link and GMSL - are available and supported by the driver. The card has two inputs and two outputs (FPD-Link only). In addition to the video interfaces it also provides a trigger signal interface and a MTD interface for FPGA firmware upload. Signed-off-by: Martin Tůma <martin.tuma@digiteqautomotive.com>
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.. SPDX-License-Identifier: GPL-2.0 | ||
==================== | ||
mgb4 iio (triggers) | ||
==================== | ||
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The mgb4 driver creates an Industrial I/O (IIO) device that provides trigger and | ||
signal level status capability. The following scan elements are available: | ||
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**activity**: | ||
The trigger levels and pending status. | ||
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| bit 1 - trigger 1 pending | ||
| bit 2 - trigger 2 pending | ||
| bit 5 - trigger 1 level | ||
| bit 6 - trigger 2 level | ||
**timestamp**: | ||
The trigger event timestamp. | ||
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The iio device can operate either in "raw" mode where you can fetch the signal | ||
levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode. | ||
In the triggered buffer mode you can follow the signal level changes (activity | ||
bits 1 and 2) using the iio device in /dev. If you enable the timestamps, you | ||
will also get the exact trigger event time that can be matched to a video frame | ||
(every mgb4 video frame has a timestamp with the same clock source). | ||
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*Note: although the activity sample always contains all the status bits, it makes | ||
no sense to get the pending bits in raw mode or the level bits in the triggered | ||
buffer mode - the values do not represent valid data in such case.* |
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.. SPDX-License-Identifier: GPL-2.0 | ||
==================== | ||
mgb4 mtd partitions | ||
==================== | ||
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The mgb4 driver creates a MTD device with two partitions: | ||
- mgb4-fw.X - FPGA firmware. | ||
- mgb4-data.X - Factory settings, e.g. card serial number. | ||
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The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is | ||
read-only. The *X* attached to the partition name represents the card number. | ||
Depending on the CONFIG_MTD_PARTITIONED_MASTER kernel configuration, you may | ||
also have a third partition named *mgb4-flash* available in the system. This | ||
partition represents the whole, unpartitioned, card's FLASH memory and one should | ||
not fiddle with it... |
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.. SPDX-License-Identifier: GPL-2.0 | ||
==================== | ||
mgb4 sysfs interface | ||
==================== | ||
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The mgb4 driver provides a sysfs interface, that is used to configure video | ||
stream related parameters (some of them must be set properly before the v4l2 | ||
device can be opened) and obtain the video device/stream status. | ||
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There are two types of parameters - global / PCI card related, found under | ||
``/sys/class/video4linux/videoX/device`` and module specific found under | ||
``/sys/class/video4linux/videoX``. | ||
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Global (PCI card) parameters | ||
============================ | ||
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**module_type** (R): | ||
Module type. | ||
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| 0 - No module present | ||
| 1 - FPDL3 | ||
| 2 - GMSL | ||
**module_version** (R): | ||
Module version number. Zero in case of a missing module. | ||
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**fw_type** (R): | ||
Firmware type. | ||
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| 1 - FPDL3 | ||
| 2 - GMSL | ||
**fw_version** (R): | ||
Firmware version number. | ||
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**serial_number** (R): | ||
Card serial number. The format is:: | ||
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PRODUCT-REVISION-SERIES-SERIAL | ||
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where each component is a 8b number. | ||
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**temperature** (R): | ||
FPGA core temperature in Celsius degree. | ||
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Common FPDL3/GMSL input parameters | ||
================================== | ||
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**input_id** (R): | ||
Input number ID, zero based. | ||
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**oldi_lane_width** (RW): | ||
Number of deserializer output lanes. | ||
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| 0 - single | ||
| 1 - dual | ||
**color_mapping** (RW): | ||
Mapping of the incoming bits in the signal to the colour bits of the pixels. | ||
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| 0 - OLDI/JEIDA | ||
| 1 - SPWG/VESA | ||
**link_status** (R): | ||
Video link status. If the link is locked, chips are properly connected and | ||
communicating at the same speed and protocol. The link can be locked without | ||
an active video stream. | ||
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| 0 - unlocked | ||
| 1 - locked | ||
**stream_status** (R): | ||
Video stream status. A stream is detected if the link is locked, the input | ||
pixel clock is running and the DE signal is moving. | ||
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| 0 - not detected | ||
| 1 - detected | ||
**vsync_status** (R): | ||
The type of VSYNC pulses as detected by the video format detector. | ||
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| 0 - active low | ||
| 1 - active high | ||
| 2 - not available | ||
**hsync_status** (R): | ||
The type of HSYNC pulses as detected by the video format detector. | ||
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| 0 - active low | ||
| 1 - active high | ||
| 2 - not available | ||
**vsync_gap_length** (RW): | ||
If the incoming video signal does not contain synchronization VSYNC and | ||
HSYNC pulses, these must be generated internally in the FPGA to achieve | ||
the correct frame ordering. This value indicates, how many "empty" pixels | ||
(pixels with deasserted Data Enable signal) are necessary to generate the | ||
internal VSYNC pulse. | ||
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**hsync_gap_length** (RW): | ||
If the incoming video signal does not contain synchronization VSYNC and | ||
HSYNC pulses, these must be generated internally in the FPGA to achieve | ||
the correct frame ordering. This value indicates, how many "empty" pixels | ||
(pixels with deasserted Data Enable signal) are necessary to generate the | ||
internal HSYNC pulse. The value must be greater than 1 and smaller than | ||
vsync_gap_length. | ||
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**pclk_frequency** (R): | ||
Input pixel clock frequency in kHz. | ||
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*Note: The frequency_range parameter must be set properly first to get | ||
a valid frequency here.* | ||
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**hsync_width** (R): | ||
Width of the HSYNC signal in PCLK clock ticks. | ||
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**vsync_width** (R): | ||
Width of the VSYNC signal in PCLK clock ticks. | ||
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**hback_porch** (R): | ||
Number of PCLK pulses between deassertion of the HSYNC signal and the first | ||
valid pixel in the video line (marked by DE=1). | ||
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**hfront_porch** (R): | ||
Number of PCLK pulses between the end of the last valid pixel in the video | ||
line (marked by DE=1) and assertion of the HSYNC signal. | ||
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**vback_porch** (R): | ||
Number of video lines between deassertion of the VSYNC signal and the video | ||
line with the first valid pixel (marked by DE=1). | ||
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**vfront_porch** (R): | ||
Number of video lines between the end of the last valid pixel line (marked | ||
by DE=1) and assertion of the VSYNC signal. | ||
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**frequency_range** (RW) | ||
PLL frequency range of the OLDI input clock generator. The PLL frequency is | ||
derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if | ||
oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to | ||
"dual". | ||
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| 0 - PLL < 50MHz | ||
| 1 - PLL >= 50MHz | ||
*Note: This parameter can not be changed while the input v4l2 device is | ||
open.* | ||
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**alignment** (RW) | ||
Pixel line alignment. Sets the pixel line alignment in bytes of the frame | ||
buffers provided via the v4l2 interface. The number must be a power of 2. | ||
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*Note: This parameter can not be changed while the input v4l2 device is | ||
open.* | ||
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Common FPDL3/GMSL output parameters | ||
=================================== | ||
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**output_id** (R): | ||
Output number ID, zero based. | ||
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**video_source** (RW): | ||
Output video source. If set to 0 or 1, the source is the corresponding card | ||
input and the v4l2 output devices are disabled. If set to 2 or 3, the source | ||
is the corresponding v4l2 video output device. | ||
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| 0 - input 0 | ||
| 1 - input 1 | ||
| 2 - v4l2 output 0 | ||
| 3 - v4l2 output 1 | ||
*Note: This parameter can not be changed while ANY of the input/output v4l2 | ||
devices is open.* | ||
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**display_width** (RW): | ||
Display width. There is no autodetection of the connected display, so the | ||
propper value must be set before the start of streaming. | ||
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*Note: This parameter can not be changed while the output v4l2 device is | ||
open.* | ||
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**display_height** (RW): | ||
Display height. There is no autodetection of the connected display, so the | ||
propper value must be set before the start of streaming. | ||
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*Note: This parameter can not be changed while the output v4l2 device is | ||
open.* | ||
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**frame_rate** (RW): | ||
Output video frame rate in frames per second. | ||
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**hsync_polarity** (RW): | ||
HSYNC signal polarity. | ||
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| 0 - active low | ||
| 1 - active high | ||
**vsync_polarity** (RW): | ||
VSYNC signal polarity. | ||
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| 0 - active low | ||
| 1 - active high | ||
**de_polarity** (RW): | ||
DE signal polarity. | ||
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| 0 - active low | ||
| 1 - active high | ||
**pclk_frequency** (RW): | ||
Output pixel clock frequency. Allowed values are between 25000-190000(kHz) | ||
and there is a non-linear stepping between two consecutive allowed | ||
frequencies. The driver finds the nearest allowed frequency to the given | ||
value and sets it. When reading this property, you get the exact | ||
frequency set by the driver. | ||
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*Note: This parameter can not be changed while the output v4l2 device is | ||
open.* | ||
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**hsync_width** (RW): | ||
Width of the HSYNC signal in PCLK clock ticks. | ||
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**vsync_width** (RW): | ||
Width of the VSYNC signal in PCLK clock ticks. | ||
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**hback_porch** (RW): | ||
Number of PCLK pulses between deassertion of the HSYNC signal and the first | ||
valid pixel in the video line (marked by DE=1). | ||
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**hfront_porch** (RW): | ||
Number of PCLK pulses between the end of the last valid pixel in the video | ||
line (marked by DE=1) and assertion of the HSYNC signal. | ||
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**vback_porch** (RW): | ||
Number of video lines between deassertion of the VSYNC signal and the video | ||
line with the first valid pixel (marked by DE=1). | ||
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**vfront_porch** (RW): | ||
Number of video lines between the end of the last valid pixel line (marked | ||
by DE=1) and assertion of the VSYNC signal. | ||
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**alignment** (RW) | ||
Pixel line alignment. Sets the pixel line alignment in bytes of the frame | ||
buffers provided via the v4l2 interface. The number must be a power of 2. | ||
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*Note: This parameter can not be changed while the output v4l2 device is | ||
open.* | ||
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*Note: This parameter can not be changed when loopback mode is active | ||
(video_source is 0 or 1). When loopback mode is enabled, the alignment is | ||
automatically set to the alignment of the input device.* | ||
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FPDL3 specific input parameters | ||
=============================== | ||
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**fpdl3_input_width** (RW): | ||
Number of deserializer input lines. | ||
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| 0 - auto | ||
| 1 - single | ||
| 2 - dual | ||
FPDL3 specific output parameters | ||
================================ | ||
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**fpdl3_output_width** (RW): | ||
Number of serializer output lines. | ||
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| 0 - auto | ||
| 1 - single | ||
| 2 - dual | ||
GMSL specific input parameters | ||
============================== | ||
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**gmsl_mode** (RW): | ||
GMSL speed mode. | ||
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| 0 - 12Gb/s | ||
| 1 - 6Gb/s | ||
| 2 - 3Gb/s | ||
| 3 - 1.5Gb/s | ||
**gmsl_stream_id** (RW): | ||
The GMSL multi-stream contains up to four video streams. This parameter | ||
selects which stream is captured by the video input. The value is the | ||
zero-based index of the stream. | ||
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*Note: This parameter can not be changed while the input v4l2 device is | ||
open.* | ||
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**gmsl_fec** (RW): | ||
GMSL Forward Error Correction (FEC). | ||
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| 0 - disabled | ||
| 1 - enabled |
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# SPDX-License-Identifier: GPL-2.0-only | ||
config VIDEO_MGB4 | ||
tristate "Digiteq Automotive MGB4 support" | ||
depends on VIDEO_DEV && PCI && I2C && DMADEVICES && SPI && MTD && IIO | ||
select VIDEOBUF2_DMA_SG | ||
select IIO_BUFFER | ||
select IIO_TRIGGERED_BUFFER | ||
select I2C_XILINX | ||
select SPI_XILINX | ||
select MTD_SPI_NOR | ||
select XILINX_XDMA | ||
help | ||
This is a video4linux driver for Digiteq Automotive MGB4 grabber | ||
cards. | ||
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To compile this driver as a module, choose M here: the | ||
module will be called mgb4. |
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# SPDX-License-Identifier: GPL-2.0 | ||
mgb4-objs := mgb4_regs.o mgb4_core.o mgb4_vin.o mgb4_vout.o \ | ||
mgb4_sysfs_pci.o mgb4_sysfs_in.o mgb4_sysfs_out.o \ | ||
mgb4_i2c.o mgb4_cmt.o mgb4_trigger.o | ||
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obj-$(CONFIG_VIDEO_MGB4) += mgb4.o |
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