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firmware: xilinx: Add pm api function for PL config reg readback
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Adds PM API for performing Programmable Logic(PL) configuration
register readback. It provides an interface to the firmware(pmufw)
to readback the FPGA configuration register.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
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Nava kishore Manne authored and intel-lab-lkp committed Oct 13, 2022
1 parent 4fe89d0 commit 53624ba
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Showing 2 changed files with 46 additions and 0 deletions.
35 changes: 35 additions & 0 deletions drivers/firmware/xilinx/zynqmp.c
Original file line number Diff line number Diff line change
Expand Up @@ -941,6 +941,41 @@ int zynqmp_pm_fpga_get_status(u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);

/**
* zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.
* @value: Buffer to store FPGA configuration status.
*
* This function provides access to the pmufw to get the FPGA configuration
* status
*
* Return: Returns status, either success or error+reason
*/
int zynqmp_pm_fpga_get_config_status(u32 *value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 buf, phys_lower_addr, phys_upper_addr, addr;
int ret;

if (!value)
return -EINVAL;

addr = (u64)&buf;

phys_lower_addr = lower_32_bits(addr);
phys_upper_addr = upper_32_bits(addr);

ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,
XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,
phys_lower_addr, phys_upper_addr,
XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,
ret_payload);

*value = ret_payload[1];

return ret;
}
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);

/**
* zynqmp_pm_pinctrl_request - Request Pin from firmware
* @pin: Pin number to request
Expand Down
11 changes: 11 additions & 0 deletions include/linux/firmware/xlnx-zynqmp.h
Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,10 @@
#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)

/* FPGA Status Reg */
#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U

/*
* Node IDs for the Error Events.
*/
Expand Down Expand Up @@ -117,6 +121,7 @@ enum pm_api_id {
PM_CLOCK_GETRATE = 42,
PM_CLOCK_SETPARENT = 43,
PM_CLOCK_GETPARENT = 44,
PM_FPGA_READ = 46,
PM_SECURE_AES = 47,
PM_FEATURE_CHECK = 63,
};
Expand Down Expand Up @@ -475,6 +480,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
int zynqmp_pm_fpga_get_config_status(u32 *value);
#else
static inline int zynqmp_pm_get_api_version(u32 *version)
{
Expand Down Expand Up @@ -745,6 +751,11 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
{
return -ENODEV;
}

int zynqmp_pm_fpga_get_config_status(u32 *value)
{
return -ENODEV;
}
#endif

#endif /* __FIRMWARE_ZYNQMP_H__ */

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