Merge pull request #7 from intel/master

Update fork

README.txt

@@ -5,9 +5,11 @@ FEB 4, 2019
 ============================================================
 
 Included in this package are:
-1. c3aib rtl (RTL implementation of AIB interface) 
+1. c3aib rtl (RTL implementation of AIB interface with no timing constrain file supplied) 
 2. CHIP AIB model. Based on AIB spec 1.0.
-3. Test bench
+3. Slave FPGA AIB model
+4. Base Test bench master c3aib connect to FPGA AIB or AIB model
+5. Test examples with different configurations 
 ===========================================================
 Revision history:
 Version 1.0: Initial release
@@ -35,18 +37,21 @@ aib_lib: c3aib files
         |-- c3aibadapt_wrap
  |--aibcr3_lib, aibcr3pnr_lib, c3aibadapt, c3dfx, and c3lib. They are related library and rtl. 
 
+maib_rtl: FPGA AIB models if user want to interop c3aib with FPGA through AIB interface.
+
 ndsimslv: simulation test bench and file list
  |-top.sv                 - Test bench file.
  |-multidie.f             - Simulation file list, include test bench and all AIB model files.
+                            See README.txt for detail in this directory.
 how2use:  example design and testbench
  |-README.txt
  |-sim_aib_top            - Test bench show 24 channel external loopback test.
  |-sim_aib_top_ncsim      - Test bench show 24 channel external loopback test with ncsim.
  |-sim_phasecom           - Test one channel loopback simulation of enabling phase compensation fifo
  |-sim_dcc                - This test show how DCC works and can correct the duty cycle to almost 50/50 from 40/60
- |-sim_modelsim           - 1 channel connects with AIB model simulated with modelsim simulator
+ |-sim_sl2ms_lpbk         - 1 channel connects with FPGA AIB model loopback test. See README.txt in this directory for detail. 
  |-sim_mod2mod            - Model to Model test. This test show how master model works with slave model
-
+maib_rtl: Stratix 10 MAIB rtl
 ============================================================
 How to compile and run simulation (VCS)
 ============================================================

aib_lib/c3aibadapt/rtl/c3aibadapt.v

@@ -22,6 +22,8 @@
 //
 //
 //-----------------------------------------------------------------------------
+
+
 module c3aibadapt (
 
   // AIB
@@ -864,7 +866,7 @@ assign fpll_shared_direct_async[2] = tb_direct_async[1];
 assign fpll_shared_direct_async[1] = tb_direct_async[0];
 assign fpll_shared_direct_async[0] = tb_direct_async[0];
 
-assign sl_sideband = {rx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[30],tx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[31], rx_ssr_parity_checker_in[29:0], tx_ssr_parity_checker_in[31:0]};
+assign sl_sideband = {avmm_hrdrst_fabric_osc_transfer_en_ssr_data, rx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[30],tx_ssr_parity_checker_in[35:32], rx_ssr_parity_checker_in[31], rx_ssr_parity_checker_in[29:0], tx_ssr_parity_checker_in[31:0]};
 
 c3aibadapt_txchnl adapt_txchnl   (/*AUTOINST*/
        // Outputs

aib_lib/c3aibadapt_wrap/rtl/aib_top.v

@@ -115,11 +115,11 @@ module aib_top
    input [31:0]                                                   i_aibaux_ctrl_bus0, //1st set of register bits from register file
    input [31:0]                                                   i_aibaux_ctrl_bus1, //2nd set of register bits from register file
    input [31:0]                                                   i_aibaux_ctrl_bus2, //3rd set of register bits from register file
-   input [9:0]                                                    i_aibaux_osc_fuse_trim, //control by Fuse/OTP from Jariet
+   input [9:0]                                                    i_aibaux_osc_fuse_trim, //control by Fuse/OTP from User
 
    //
-   input                                                          i_osc_bypclk,     // test clock from c4 bump, may tie low for Jariet if not used
-   output                                                         o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, Jariet may use this clock to connect with i_test_clk_1g
+   input                                                          i_osc_bypclk,     // test clock from c4 bump, may tie low for User if not used
+   output                                                         o_aibaux_osc_clk, // osc clk output to test C4 bump to characterize the oscillator, User may use this clock to connect with i_test_clk_1g
     //======================================================================================
    // DFT signals
    input                                                          i_scan_clk,     //ATPG Scan shifting clock from Test Pad.  
@@ -150,12 +150,12 @@ module aib_top
 
    input [2:0]                                                    i_aibdft2osc,  //To AIB osc.[2] force reset [1] force enable [0] 33 MHz JTAG
    output [12:0]                                                  o_aibdft2osc,  //Observability of osc and DLL/DCC status 
-                                                                                 //this signal go through C4 bump, Jariet may muxed it out with their test signals
+                                                                                 //this signal go through C4 bump, User may muxed it out with their test signals
 
    //output TCB 
    output                                                         o_last_bs_out, //last boundary scan chain output, TDO 
 
-   output                                                         o_por, // S10 POR to Jariet, can be left unconnected for Jariet
+   output                                                         o_por, // S10 POR to User, can be left unconnected for User
    output                                                         o_osc_monitor, //Output from oscillator, go to pinmux block before go to C4 test bump