The shift register bits are not ported up in the model, therefore the user-defined bits can not be written

[sabedin01]

At the aib_channel level we will need to have ms_data_fr_core and sl_data_fr_core be input of 81 bits and 73 bits as defined in the spec.
Otherwise the user field bits of the shift register can not be used form this model.

Please refer to 2.2.2 Sideband Control Signals section and table 11 in the spec 1.1

[xinyang2k]

We just updated the model to pull out the user-defined bits for shift registers.