vISA: support platforms ARL and XE2

Add platforms Xe_ARL and Xe2 to vISA::TARGET_PLATFORM

inc/common/sku_wa_defs.h

@@ -626,3 +626,9 @@ SPDX-License-Identifier: MIT
         "Workaround",
         WA_BUG_TYPE_UNKNOWN,
         WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN)
+
+        WA_DECLARE(
+        Wa_22017182272,
+        "Workaround",
+        WA_BUG_TYPE_UNKNOWN,
+        WA_BUG_PERF_IMPACT_UNKNOWN, WA_COMPONENT_UNKNOWN)

visa/BinaryEncodingIGA.cpp

@@ -361,12 +361,16 @@ BinaryEncodingIGA::getIGAInternalPlatform(TARGET_PLATFORM genxPlatform) {
     break;
   case Xe_DG2:
   case Xe_MTL:
+  case Xe_ARL:
     platform = Platform::XE_HPG;
     break;
   case Xe_PVC:
   case Xe_PVCXT:
     platform = Platform::XE_HPC;
     break;
+  case Xe2:
+    platform = Platform::XE2;
+    break;
   default:
     break;
   }
@@ -1679,8 +1683,17 @@ SendDesc BinaryEncodingIGA::encodeExDescRegA0(G4_INST *sendInst,
   const bool isLscBti = isLsc && descG4->getLscAddrType() == LSC_ADDR_TYPE_BTI;
   const bool isUgm = sendInst->getMsgDesc()->getSFID() == vISA::SFID::UGM;
   encodeExBso &= !isLscBti;
+  encodeExBso &= (platform < Xe2 || !isUgm);
   if (encodeExBso)
     sdos.extraOpts.add(InstOpt::EXBSO);
+  if (isLsc && isUgm && !encodeExBso) {
+    bool isLscBssOrSs = descG4->getLscAddrType() == LSC_ADDR_TYPE_BSS ||
+                        descG4->getLscAddrType() == LSC_ADDR_TYPE_SS;
+    if (isLscBssOrSs && descG4->getBti() != nullptr) {
+      // BSS/SS with a0 reg (ExDesc.IsReg) with UGM
+      sdos.exDescImmOff = descG4->getExDescImmOff();
+    }
+  }
 
   // G4 IR keeps Src1.Length (xlen) separate.  So it's known,
   // (even with a reg desc in nonExBSO mode)

visa/BuildIR.h

@@ -2096,8 +2096,16 @@ class IR_Builder {
   G4_SrcRegRegion *lscLoadEffectiveAddress(
       LSC_OP lscOp, LSC_SFID lscSfid, G4_Predicate *pred, G4_ExecSize execSize,
       VISA_EMask_Ctrl execCtrl, LSC_ADDR addrInfo, int bytesPerDataElem,
-      const G4_Operand *surface, G4_SrcRegRegion *addr, uint32_t &exDesc
-  );
+      const G4_Operand *surface, G4_SrcRegRegion *addr, uint32_t &exDesc,
+      uint32_t &exDescImmOff);
+
+  // try and promote an immediate offset to LSC descriptor
+  // (doesn't work for block2d)
+  bool lscTryPromoteImmOffToExDesc(LSC_OP lscOp, LSC_SFID lscSfid,
+                                   LSC_ADDR addrInfo, int bytesPerDataElem,
+                                   const G4_Operand *surface,
+                                   uint32_t &exDescImm, uint32_t &exDescImmOff);
+
   G4_SrcRegRegion *lscCheckRegion(G4_Predicate *pred, G4_ExecSize execSize,
                                   VISA_EMask_Ctrl execCtrl,
                                   G4_SrcRegRegion *src);
@@ -2331,6 +2339,23 @@ class IR_Builder {
                                 bool isNativeSIMDSize, bool isFP16Return,
                                 bool isFP16Input) const;
 };
+
+constexpr VISALscImmOffOpts getLscImmOffOpt(LSC_ADDR_TYPE addrType) {
+  switch (addrType) {
+  case LSC_ADDR_TYPE_FLAT:
+    return VISA_LSC_IMMOFF_ADDR_TYPE_FLAT;
+  case LSC_ADDR_TYPE_BSS:
+    return VISA_LSC_IMMOFF_ADDR_TYPE_BSS;
+  case LSC_ADDR_TYPE_SS:
+    return VISA_LSC_IMMOFF_ADDR_TYPE_SS;
+  case LSC_ADDR_TYPE_BTI:
+  case LSC_ADDR_TYPE_ARG:
+    return VISA_LSC_IMMOFF_ADDR_TYPE_BTI;
+  default:
+    break;
+  }
+  return VISA_LSC_IMMOFF_INVALID;
+}
 } // namespace vISA
 
 // G4IR instructions added by JIT that do not result from lowering

visa/BuildIRImpl.cpp

@@ -2518,6 +2518,12 @@ G4_SendDescRaw *IR_Builder::createLscMsgDesc(
     }
   }
 
+  uint32_t exDescImmOff = 0;
+  if (lscTryPromoteImmOffToExDesc(op, lscSfid, addr, dataSizeBits / 8, surface,
+                                  exDesc, exDescImmOff)) {
+    addr.immOffset = 0;
+  }
+
   vISA_ASSERT(addr.immOffset == 0, "invalid address immediate offset");
 
   SFID sfid = LSC_SFID_To_SFID(lscSfid);
@@ -2566,6 +2572,9 @@ G4_SendDescRaw *IR_Builder::createLscMsgDesc(
 
   G4_SendDescRaw *g4desc =
       createSendMsgDesc(sfid, desc, exDesc, src1Len, access, surface);
+  if (exDescImmOff) {
+    g4desc->setExDescImmOff(exDescImmOff);
+  }
   g4desc->setLdStAttr(otherAttrs);
   return g4desc;
 }
@@ -3279,6 +3288,8 @@ void IR_Builder::doSimplification(G4_INST *inst) {
   // - indices to src are all within src.
   // - destination stride in bytes must be equal to the source element size in
   // bytes.
+
+  // - both src and dst are dword data type:
   bool canConvertMovToMovi =
       inst->opcode() == G4_mov && inst->getExecSize() == g4::SIMD8 &&
       inst->isRawMov() && inst->getDst() &&
@@ -3290,6 +3301,11 @@ void IR_Builder::doSimplification(G4_INST *inst) {
       inst->getSrc(0)->getTypeSize() ==
           inst->getDst()->getTypeSize() *
               inst->getDst()->asDstRegRegion()->getHorzStride();
+  if (getPlatform() >= Xe2) {
+    canConvertMovToMovi = canConvertMovToMovi &&
+                          IS_DTYPE(inst->getDst()->getType()) &&
+                          IS_DTYPE(inst->getSrc(0)->getType());
+  }
   if (canConvertMovToMovi) {
     // Convert 'mov' to 'movi' if the following conditions are met.
 

visa/CISA.l

@@ -466,6 +466,13 @@ lsc_atomic_iinc|lsc_atomic_idec|lsc_atomic_iadd|lsc_atomic_load|lsc_atomic_store
         return LSC_ATOMIC_MNEMONIC;
     }
 
+lsc_apndctr_atomic_add|lsc_apndctr_atomic_sub|lsc_apndctr_atomic_store {
+      TRACE("** lsc_apndctr_atomic INST");
+      CISAlval.lsc_subOpcode = str2lscop(yytext);
+      // this is set in the parser based on the SFID
+      // CISAlval.lsc_opcode = ISA_LSC_UNTYPED;
+      return LSC_ATOMIC_MNEMONIC;
+    }
 
 lsc_read_state_info {
         TRACE("** lsc_read_state_info INST");
@@ -733,15 +740,30 @@ sample_3d|sample_b|sample_l|sample_c|sample_d|sample_b_c|sample_l_c|sample_d_c|s
         return SAMPLE_3D_OP;
     }
 
+sample_po|sample_po_b|sample_po_l|sample_po_c|sample_po_d|sample_po_l_c|sample_po_lz|sample_po_c_lz {
+        TRACE("** SAMPLE_3D");
+        CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
+        return SAMPLE_3D_OP;
+    }
 
-
+sample_mlod|sample_c_mlod|sample_d_c_mlod {
+        TRACE("** SAMPLE_3D");
+        CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
+        return SAMPLE_3D_OP;
+    }
 
 load_3d|load_mcs|load_2dms_w|load_lz {
         TRACE("** LOAD_3D");
         CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
         return LOAD_3D_OP;
     }
 
+load_l {
+        TRACE("** LOAD_3D");
+        CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
+        return LOAD_3D_OP;
+    }
+
 sample4|sample4_c {
         TRACE("** SAMPLE4_3D");
         CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
@@ -754,7 +776,17 @@ sample4_po|sample4_po_c {
         return SAMPLE4_3D_OP;
     }
 
+sample4_po_b|sample4_po_l|sample4_po_l_c|sample4_po_i|sample4_po_i_c {
+        TRACE("** SAMPLE4_3D");
+        CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
+        return SAMPLE4_3D_OP;
+    }
 
+sample4_i|sample4_l|sample4_b|sample4_i_c|sample4_l_c {
+        TRACE("** SAMPLE4_3D");
+        CISAlval.sample3DOp = str2SampleOpcode(yytext, pBuilder->getPlatform());
+        return SAMPLE4_3D_OP;
+    }
 
 resinfo {
         TRACE("** RESINFO_3D");
@@ -1078,6 +1110,8 @@ type[ ]*=[ ]*(ud|d|uw|w|ub|b|df|f|bool|uq|q|UD|D|UW|W|UB|B|DF|F|Bool|BOOL|UQ|Q|h
             CISAlval.lsc_caching_opt = LSC_CACHING_WRITETHROUGH;
         } else if (strcmp(yytext+1,"st") == 0) {
             CISAlval.lsc_caching_opt = LSC_CACHING_STREAMING;
+        } else if (strcmp(yytext+1,"cc") == 0) {
+            CISAlval.lsc_caching_opt = LSC_CACHING_CONSTCACHED;
         } else { /* ri */
             CISAlval.lsc_caching_opt = LSC_CACHING_READINVALIDATE;
         }

visa/CISA.y

@@ -250,6 +250,11 @@ std::vector<attr_gen_struct*> AttrOptVar;
         VISA_opnd             *surface; // can be imm or reg
         int                    surfaceIndex;
     } lsc_addr_model;
+    struct {
+        VISA_opnd *reg;
+        LSC_DATA_SHAPE_TYPED_BLOCK2D shape_typed2d;
+    } lsc_data_operand_typed2d;
+    LSC_DATA_SHAPE_TYPED_BLOCK2D lsc_data_shape_typed2d;
 
     // Align Support in Declaration
     VISA_Align             align;

visa/Common_ISA.cpp

@@ -69,24 +69,80 @@ static const char *getSampleOp3DNameOrNull(VISASampler3DSubOpCode opcode,
     return "sampleinfo";
   case VISA_3D_SAMPLE_KILLPIX: // 0xC
     return "sample+killpix";
+  case VISA_3D_GATHER4_L: // 0xD
+    return "sample4_l";
+  case VISA_3D_GATHER4_B: // 0xE
+    return "sample4_b";
+  case VISA_3D_GATHER4_I: // 0xF
+    return "sample4_i";
   case VISA_3D_GATHER4_C: // 0x10
     return "sample4_c";
   case VISA_3D_GATHER4_PO: // 0x11
+                           // Xe2 reuses GATHER4_PO* opcode values, Xe2 doesn't
+                           // have GATHER4_PO*.
+    vISA_ASSERT(VISA_3D_SAMPLE_D_C_MLOD == VISA_3D_GATHER4_PO,
+                "Code below needs update");
+    if (platform >= Xe2) {
+      return "sample_d_c_mlod";
+    }
     return "sample4_po";
   case VISA_3D_GATHER4_PO_C: // 0x12
+    vISA_ASSERT(VISA_3D_SAMPLE_MLOD == VISA_3D_GATHER4_PO_C,
+                "Code below needs update");
+    if (platform >= Xe2) {
+      return "sample_mlod";
+    }
     return "sample4_po_c";
+  case VISA_3D_SAMPLE_C_MLOD: // 0x13
+    return "sample_c_mlod";
   case VISA_3D_SAMPLE_D_C: // 0x14
     return "sample_d_c";
+  case VISA_3D_GATHER4_I_C: // 0x15
+    return "sample4_i_c";
+  case VISA_3D_GATHER4_L_C: // 0x17
+    return "sample4_l_c";
   case VISA_3D_SAMPLE_LZ: // 0x18
     return "sample_lz";
   case VISA_3D_SAMPLE_C_LZ: // 0x19
     return "sample_c_lz";
   case VISA_3D_LD_LZ: // 0x1A
     return "load_lz";
+  case VISA_3D_LD_L: // 0x1B
+    return "load_l";
   case VISA_3D_LD2DMS_W: // 0x1C
     return "load_2dms_w";
   case VISA_3D_LD_MCS: // 0x1D
     return "load_mcs";
+  case VISA_3D_SAMPLE_PO:
+    return "sample_po";
+  case VISA_3D_SAMPLE_PO_B:
+    return "sample_po_b";
+  case VISA_3D_SAMPLE_PO_L:
+    return "sample_po_l";
+  case VISA_3D_SAMPLE_PO_C:
+    return "sample_po_c";
+  case VISA_3D_SAMPLE_PO_D:
+    return "sample_po_d";
+  case VISA_3D_SAMPLE_PO_L_C:
+    return "sample_po_l_c";
+  case VISA_3D_GATHER4_PO_PACKED:
+    return "sample4_po";
+  case VISA_3D_GATHER4_PO_PACKED_L:
+    return "sample4_po_l";
+  case VISA_3D_GATHER4_PO_PACKED_B:
+    return "sample4_po_b";
+  case VISA_3D_GATHER4_PO_PACKED_I:
+    return "sample4_po_i";
+  case VISA_3D_GATHER4_PO_PACKED_C:
+    return "sample4_po_c";
+  case VISA_3D_GATHER4_PO_PACKED_I_C:
+    return "sample4_po_i_c";
+  case VISA_3D_GATHER4_PO_PACKED_L_C:
+    return "sample4_po_l_c";
+  case VISA_3D_SAMPLE_PO_LZ:
+    return "sample_po_lz";
+  case VISA_3D_SAMPLE_PO_C_LZ:
+    return "sample_po_c_lz";
   default:
     return nullptr;
   }

visa/Common_ISA_util.cpp

@@ -1393,6 +1393,17 @@ const raw_opnd &getRawOperand(const CISA_INST *inst, unsigned i) {
   return inst->opnd_array[i]->_opnd.r_opnd;
 }
 
+bool isNullRawOperand(const CISA_INST *inst, unsigned i) {
+  vISA_ASSERT(inst, "Argument Exception: argument inst is NULL.");
+  vISA_ASSERT(inst->opnd_num > i,
+               "No such operand, i, for instruction inst.");
+  return inst->opnd_array[i]->_opnd.r_opnd.index == 0;
+}
+
+bool isNotNullRawOperand(const CISA_INST *inst, unsigned i) {
+  return !isNullRawOperand(inst, i);
+}
+
 const vector_opnd &getVectorOperand(const CISA_INST *inst, unsigned i) {
   vISA_ASSERT(inst, "Argument Exception: argument inst is NULL.");
   vISA_ASSERT(inst->opnd_num > i,
@@ -1595,6 +1606,21 @@ LSC_CACHE_OPTS convertLSCLoadStoreCacheControlEnum(LSC_L1_L3_CC L1L3cc,
     else
       cacheOpts = {LSC_CACHING_WRITEBACK, LSC_CACHING_WRITEBACK};
     break;
+  case LSC_L1UC_L3CC:
+    if (isLoad) {
+      cacheOpts = {LSC_CACHING_UNCACHED, LSC_CACHING_CONSTCACHED};
+      break;
+    }
+  case LSC_L1C_L3CC:
+    if (isLoad) {
+      cacheOpts = {LSC_CACHING_CACHED, LSC_CACHING_CONSTCACHED};
+      break;
+    }
+  case LSC_L1IAR_L3IAR:
+    if (isLoad) {
+      cacheOpts = {LSC_CACHING_READINVALIDATE, LSC_CACHING_READINVALIDATE};
+      break;
+    }
   default:
     vISA_ASSERT_UNREACHABLE("unsupported caching option");
     break;

visa/Common_ISA_util.h

@@ -111,6 +111,9 @@ template <typename T> T getPrimitiveOperand(const CISA_INST *inst, unsigned i) {
 
 const raw_opnd &getRawOperand(const CISA_INST *inst, unsigned i);
 
+bool isNullRawOperand(const CISA_INST *inst, unsigned i);
+bool isNotNullRawOperand(const CISA_INST *inst, unsigned i);
+
 const vector_opnd &getVectorOperand(const CISA_INST *inst, unsigned i);
 
 CISA_opnd_type getOperandType(const CISA_INST *inst, unsigned i);

visa/G4_BB.cpp

@@ -588,6 +588,10 @@ int G4_BB::getConflictTimesForTGL(std::ostream &output, int *firstRegCandidate,
 
       if (reducedBundles) {
         bundleID = (firstRegCandidate[i] % 16) / 2;
+      }
+      if (parent->builder->has64bundleSize2GRFPerBank()) {
+        bankID = (firstRegCandidate[i] % 4) / 2;
+        bundleID = (firstRegCandidate[i] % 32) / 4;
       }
        // Same bank and same bundle
       if (bundles[bankID][bundleID] != -1) {
@@ -895,13 +899,27 @@ static bool hasInternalConflict(IR_Builder *builder, int reg1, int reg2) {
     bankID2 = (reg2 % 4) / 2;
   }
 
+  if (builder->has64bundleSize2GRFPerBank()) {
+    bundleID1 = (reg1 % 32) / 4;
+    bankID1 = (reg1 % 4) / 2;
+    bundleID2 = (reg2 % 32) / 4;
+    bankID2 = (reg2 % 4) / 2;
+  }
+
   if (builder->hasOneGRFBank16Bundles()) {
     bundleID1 = (reg1 % 64) / 4;
     bankID1 = reg1 % 2;
     bundleID2 = (reg2 % 64) / 4;
     bankID2 = reg2 % 2;
   }
 
+  if (builder->has64bundleSize()) {
+    bundleID1 = (reg1 % 16) / 2;
+    bankID1 = reg1 % 2;
+    bundleID2 = (reg2 % 16) / 2;
+    bankID2 = reg2 % 2;
+  }
+
   return ((bankID1 == bankID2) && (bundleID1 == bundleID2));
 }