Skip to content

Commit

Permalink
[LIBCLC] Extend __CLC_NVVM_ATOMIC with generic AS (#7221)
Browse files Browse the repository at this point in the history 
The diffs don't show it very well, but this patch extends
`__CLC_NVVM_ATOMIC` macro to generate one more overload, targetting a
generic address space, while at it, it also fixes a mangled name used in
the implementation of `__CLC_NVVM_ATOMIC_IMPL_SUBSTITUTION`.
  • Loading branch information
@jchlanda
jchlanda committed Nov 14, 2022
1 parent 20b1f1c commit d6a8fd1
Showing 1 changed file with 53 additions and 53 deletions.
106 changes: 53 additions & 53 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,62 +72,62 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
} \
}

#define __CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, NAME_MANGLED, ADDR_SPACE, \
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
_CLC_DECL TYPE \
NAME_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = semantics & 0x1F; \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
break; \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
#define __CLC_NVVM_ATOMIC_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, NAME_MANGLED, \
ADDR_SPACE, POINTER_AND_ADDR_SPACE_MANGLED, ADDR_SPACE_NV, SUBSTITUTION) \
__attribute__((always_inline)) _CLC_DECL TYPE \
NAME_MANGLED##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv\
5Scope4FlagENS##SUBSTITUTION##_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = semantics & 0x1F; \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
break; \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
}

#define __CLC_NVVM_ATOMIC(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __global, AS1, _global_) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __local, AS3, _shared_)

NAME_MANGLED, __global, PU3AS1, _global_, 1) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, __local, PU3AS3, _shared_, 1) \
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
NAME_MANGLED, , P, _gen_, 0)
#endif

0 comments on commit d6a8fd1

Please sign in to comment.