ICX: Release v1.21 event files

This commit releases ICX v1.21 events and updates mapfile.csv
accordingly.

ICX/events/icelakex_core.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.20",
-    "DatePublished": "04/05/2023",
-    "Version": "1.20",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.21",
+    "DatePublished": "06/06/2023",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [
@@ -2147,8 +2147,32 @@
       "EventCode": "0x80",
       "UMask": "0x04",
       "EventName": "ICACHE_16B.IFDATA_STALL",
-      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-      "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
+      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]",
+      "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "500009",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x80",
+      "UMask": "0x04",
+      "EventName": "ICACHE_DATA.STALLS",
+      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]",
+      "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "500009",
@@ -2219,8 +2243,32 @@
       "EventCode": "0x83",
       "UMask": "0x04",
       "EventName": "ICACHE_64B.IFTAG_STALL",
-      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-      "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
+      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
+      "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x83",
+      "UMask": "0x04",
+      "EventName": "ICACHE_TAG.STALLS",
+      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
+      "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "200003",
@@ -2387,8 +2435,32 @@
       "EventCode": "0x87",
       "UMask": "0x01",
       "EventName": "ILD_STALL.LCP",
-      "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-      "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
+      "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]",
+      "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
+      "Counter": "0,1,2,3",
+      "PEBScounters": "0,1,2,3",
+      "SampleAfterValue": "500009",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0",
+      "Speculative": "1"
+    },
+    {
+      "EventCode": "0x87",
+      "UMask": "0x01",
+      "EventName": "DECODE.LCP",
+      "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
+      "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "500009",

ICX/events/icelakex_uncore.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.20",
-    "DatePublished": "04/05/2023",
-    "Version": "1.20",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.21",
+    "DatePublished": "06/06/2023",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [

ICX/events/icelakex_uncore_experimental.json

@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.20",
-    "DatePublished": "04/05/2023",
-    "Version": "1.20",
+    "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.21",
+    "DatePublished": "06/06/2023",
+    "Version": "1.21",
     "Legend": ""
   },
   "Events": [
@@ -17553,7 +17553,7 @@
       "UMaskExt": "0x00",
       "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
       "BriefDescription": "Message Held : Parallel Success",
-      "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle",
+      "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel",
       "Counter": "0,1,2",
       "MSRValue": "0x00",
       "ELLC": "0",

mapfile.csv

@@ -119,11 +119,11 @@ GenuineIntel-6-8F,V1.13,/SPR/events/sapphirerapids_core.json,core,,,
 GenuineIntel-6-8F,V1.13,/SPR/events/sapphirerapids_uncore.json,uncore,,,
 GenuineIntel-6-8F,V1.13,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-CF,V1.13,/SPR/events/sapphirerapids_core.json,core,,,
-GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_core.json,core,,,
-GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_uncore.json,uncore,,,
-GenuineIntel-6-6A,V1.20,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
-GenuineIntel-6-6C,V1.20,/ICX/events/icelakex_core.json,core,,,
-GenuineIntel-6-6C,V1.20,/ICX/events/icelakex_uncore.json,uncore,,,
+GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_core.json,core,,,
+GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore.json,uncore,,,
+GenuineIntel-6-6A,V1.21,/ICX/events/icelakex_uncore_experimental.json,uncore experimental,,,
+GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_core.json,core,,,
+GenuineIntel-6-6C,V1.21,/ICX/events/icelakex_uncore.json,uncore,,,
 GenuineIntel-6-96,V1.04,/EHL/events/elkhartlake_core.json,core,,,
 GenuineIntel-6-9C,V1.04,/EHL/events/elkhartlake_core.json,core,,,
 GenuineIntel-6-97,V1.21,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom