Triple equals === in ROHD

[quekyj]

1. Missing triple equal in ROHD. Double equal and triple equal are different. Triple equals can compare x to x, z to z. Triple equals will be seen in the analog behavioral code which they can compare x vs z which you use triple equal. If both side x considers true in triple equal, if both side x, output is still x.

2. If the triple equal is needed, then we will need to have !== as well (Triple not equal)

[mkorbel1]

ROHD takes a different approach to how signals, values, and equality checks work than SystemVerilog.

Comparing the values of two Logic signals in a synthesizable way is done using Logic.eq. This will always represent a synthesizable comparison. In simulation, if either value is not valid, the resulting equality check will also be invalid.

Comparing whether two Logic objects are exactly the same is done using Logic.==. This is a pure-software object reference comparison.

Comparing whether two LogicValues have the same value is done using LogicValue.==. This checks that every bit of the value is identical, including invalid bits like x and z. Note that LogicValue is sort of like an arbitrary width, 4-value, immutable primitive. LogicValues are a software construct, and aren't synthesizable signals.

There's also LogicValue.eq, which will behave similarly to Logic.eq in that if any bit in either of the objects being compared is invalid, the result will also be invalid.

These mechanisms for comparison make it easy to tell when you're dealing with a value versus a signal, and hard to accidentally use something non-synthesizable in a hardware design.