Arithmetic shift-right generated SV can be ineffective depending on nearby logic

[mkorbel1]

Describe the bug

If an unsigned operation is applied to the result of an arithmetic shift-right in the generated SystemVerilog, it may perform as a logical (unsigned) right-shift instead.

For example, if generated SystemVerilog looks like this:

  assign x = {32{c}} & ($signed(a) >>> b) ;

This actually performs an unsigned shift right.

To Reproduce

Perform an unsigned bitwise operation on the result of an arithmetic shift-right.

Expected behavior

Generated verilog for arithmetic shift right is consistent always.

Actual behavior

Depending on surrounding logic, a logical shift-right may occur instead.

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

Present in v0.4.2

[saw235]

Can you try this one? Note the curly braces instead of the parenthesis.

 assign x = {32{c}} & {$signed(a) >>> b} ;

The reason for this is because the curly braces makes it self-determined. I suspect that the & operator causes it to think that the result type should be unsigned and thus the arithmetic shift makes a zero extend.

[mkorbel1]

Can you try this one? Note the curly braces instead of the parenthesis.

 assign x = {32{c}} & {$signed(a) >>> b} ;

The reason for this is because the curly braces makes it self-determined. I suspect that the & operator causes it to think that the result type should be unsigned and thus the arithmetic shift makes a zero extend.

Good call @saw235, I like this better. Tests pass, updated PR with that adjusted. Look good to you?
#296