Fix #295, signed arithmetic shift right #296
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Description & Motivation
Shift-right arithmetic (SRA) is broken in generated SystemVerilog if an unsigned operation is applied to the result (see #295)
This fix maintains that the SystemVerilog still uses
>>>so that it is similar to the original implementation but adds an additional set of{}around the result to guarantee safety.Thank you to @saw235 for the implementation suggestion in #295 (comment)
Related Issue(s)
Fix #295
Testing
Added a new test that failed before the fix.
Backwards-compatibility
No
Documentation
No