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t507: cpu on
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@iuncuim
iuncuim committed Dec 22, 2022
1 parent 899748c commit c12d078
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Showing 3 changed files with 33 additions and 21 deletions.
43 changes: 26 additions & 17 deletions plat/allwinner/common/sunxi_cpu_ops.c
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Expand Up @@ -54,7 +54,7 @@ static void sunxi_cpu_off(u_register_t mpidr)
VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);

/* Deassert DBGPWRDUP */
//mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
/* Activate the core output clamps, but not for core 0. */
if (core != 0)
mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
Expand All @@ -71,23 +71,32 @@ void sunxi_cpu_on(u_register_t mpidr)

VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);

/* Assert CPU core reset */
mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
/* Assert CPU power-on reset */
mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Set CPU to start in AArch64 mode */
mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
BIT(SUNXI_AA64nAA32_OFFSET + core));
/* Apply power to the CPU */
mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), 0x1);
mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), 0x1);
mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), 0x1);
sunxi_cpu_enable_power(cluster, core);
/* Release the core output clamps */
mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
/* Deassert CPU power-on reset */
mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Deassert CPU core reset */
mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
/* Assert DBGPWRDUP */
//mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), 0x2);
mmio_setbits_32(SUNXI_CPU_UNK_REG(core), 0x1);
mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), 0x1);
mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), 0x100);

// /* Assert CPU core reset */
// mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
// /* Assert CPU power-on reset */
// mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
// /* Set CPU to start in AArch64 mode */
// mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
// BIT(SUNXI_AA64nAA32_OFFSET + core));
// /* Apply power to the CPU */
// sunxi_cpu_enable_power(cluster, core);
// /* Release the core output clamps */
// mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
// /* Deassert CPU power-on reset */
// mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
// /* Deassert CPU core reset */
// mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
// /* Assert DBGPWRDUP */
// mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
}

void sunxi_cpu_power_off_others(void)
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9 changes: 6 additions & 3 deletions plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
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Expand Up @@ -13,16 +13,19 @@
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010 + (c) * 0x10)
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014 + (c) * 0x10)
#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
/*#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)*/
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
#define SUNXI_C0_CPU_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0060 + (c) * 4)

#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000 + (c) * 4)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
#define SUNXI_CPU_CTRL_REG(c) (SUNXI_CPUSUBSYS_BASE + 0x0020 + (c) * 4)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x0044 + (n) * 8)

#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_CPU_UNK_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0070 + (c) * 4)

#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
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2 changes: 1 addition & 1 deletion plat/allwinner/sun50i_h616/include/sunxi_mmap.h
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Expand Up @@ -41,7 +41,7 @@
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_I2C_BASE 0x07081400
#define SUNXI_R_RSB_BASE 0x07083000
#define SUNXI_CPUCFG_BASE 0x08100000
#define SUNXI_CPUSUBSYS_BASE 0x08100000
#define SUNXI_C0_CPUXCFG_BASE 0x09010000

#endif /* SUNXI_MMAP_H */

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