Merge 3886867 into 2a8d953

examples/fifo_wide_handshake_1.lua

@@ -17,7 +17,7 @@ local p100 = RM.makeHandshake( RM.map( C.plus100(types.uint(8)), T) )
 ------------
 ITYPE = types.array2d( types.uint(8), T )
 local inp = R.input( R.Handshake(ITYPE) )
-local regs = { R.instantiateRegistered("f1", RM.fifo(ITYPE,128,nil,W,H,T) ) }
+local regs = { R.instantiate("f1", RM.fifo(ITYPE,128,nil,W,H,T) ) }
 
 ------
 local pinp = R.applyMethod("l1",regs[1],"load")

examples/fifo_wide_handshake_2.lua

@@ -9,15 +9,12 @@ W = 128
 H = 64
 T = 8
 
---inp = S.parameter("inp",types.uint(8))
---plus100 = RM.lift( "plus100", types.uint(8), types.uint(8) , 10, terra( a : &uint8, out : &uint8  ) @out =  @a+100 end, inp, inp + S.constant(100,types.uint(8)) )
-
 ------------
 local p100 = RM.makeHandshake( RM.map( C.plus100(types.uint(8)), T) )
 ------------
 ITYPE = types.array2d( types.uint(8), T )
 local inp = R.input( R.Handshake(ITYPE) )
-local regs = {R.instantiateRegistered("f1", RM.fifo(ITYPE,128)), R.instantiateRegistered("f2", RM.fifo(ITYPE,128)) }
+local regs = {R.instantiate("f1", RM.fifo(ITYPE,128)), R.instantiate("f2", RM.fifo(ITYPE,128)) }
 ------
 local pinp = R.applyMethod("l1",regs[1],"load")
 local out = R.apply( "plus100", p100, pinp )

examples/fifo_wide_handshake_bram.lua

@@ -9,15 +9,12 @@ W = 128
 H = 64
 T = 8
 
---inp = S.parameter("inp",types.uint(8))
---plus100 = RM.lift( "plus100", types.uint(8), types.uint(8) , 10, terra( a : &uint8, out : &uint8  ) @out =  @a+100 end, inp, inp + S.constant(100,types.uint(8)) )
-
 ------------
 local p100 = RM.makeHandshake( RM.map( C.plus100(types.uint(8)), T) )
 ------------
 ITYPE = types.array2d( types.uint(8), T )
 local inp = R.input( R.Handshake(ITYPE) )
-local regs = {R.instantiateRegistered("f1",RM.fifo(ITYPE,256))}
+local regs = {R.instantiate("f1",RM.fifo(ITYPE,256))}
 
 ------
 local pinp = R.applyMethod("l1",regs[1],"load")

examples/fifo_wide_handshake_noop.lua

@@ -17,7 +17,7 @@ local p100 = RM.makeHandshake(RM.map( C.plus100(types.uint(8)), T))
 ------------
 ITYPE = types.array2d( types.uint(8), T )
 local inp = R.input( R.Handshake(ITYPE) )
-local regs = {R.instantiateRegistered("f1",RM.fifo(ITYPE,1,false,W,H,T,true))}
+local regs = {R.instantiate("f1",RM.fifo(ITYPE,1,false,W,H,T,true))}
 
 ------
 local pinp = R.applyMethod("l1",regs[1],"load")

examples/makefile

@@ -18,7 +18,7 @@ ZU9VIVADOSOC += $(patsubst %.lua,$(BUILDDIR)/%.zu9vivadoSOC.correct.txt,$(SRCS_S
 ZU9VIVADOSOC += $(patsubst %.lua,$(BUILDDIR)/%.zu9vivadoSOC.regcorrect.txt,$(SRCS_SOC))
 
 SRCS = $(wildcard *.lua)
-SRCS := $(filter-out harness.lua examplescommon.lua pyramid_core.lua harris_core.lua sift_core.lua sift_core_hw.lua campipe_core.lua descriptor_core.lua  stereo_core.lua stereo_tr_core.lua  lk_core.lua lk_tr_core.lua $(SRCS_SOC) harnessSOC.lua,$(SRCS))
+SRCS := $(filter-out pyramid_core.lua harris_core.lua sift_core.lua sift_core_hw.lua campipe_core.lua descriptor_core.lua  stereo_core.lua stereo_tr_core.lua  lk_core.lua lk_tr_core.lua $(SRCS_SOC),$(SRCS))
 METADATA = $(patsubst %.lua,$(BUILDDIR)/%.metadata.lua,$(SRCS))
 
 RIGEL_VERILATOR_INCLUDE ?= $(shell pkg-config --variable=includedir verilator)

examples/soc_15x15.lua

@@ -7,8 +7,9 @@ local RS = require "rigelSimple"
 local RM = require "modules"
 require "types".export()
 local types = require "types"
+local SDF = require "sdf"
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,256}):instantiate()
 
 ------------
 inp = R.input( types.uint(8) )

examples/soc_15x15x15.lua

@@ -7,8 +7,9 @@ local RS = require "rigelSimple"
 local RM = require "modules"
 require "types".export()
 local types = require "types"
+local SDF = require "sdf"
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,240}):instantiate()
 
 ------------
 inp = R.input( types.uint(8) )

examples/soc_2in.lua

@@ -6,8 +6,9 @@ local RS = require "rigelSimple"
 local RM = require "modules"
 local G = require "generators"
 require "types".export()
+local SDF = require "sdf"
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
 
 local inp = R.input(R.HandshakeTrigger)
 local inp0, inp1 = RS.fanOut{input=inp,branches=2}

examples/soc_arbiter.lua

@@ -5,9 +5,10 @@ local harness = require "harnessSOC"
 local G = require "generators"
 local RS = require "rigelSimple"
 local types = require "types"
+local SDF = require "sdf"
 types.export()
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
 
 OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
   function(i)

examples/soc_convgen.lua

@@ -4,17 +4,18 @@ local SOC = require "soc"
 local harness = require "harnessSOC"
 local RS = require "rigelSimple"
 local C = require "examplescommon"
+local SDF = require "sdf"
 require "generators".export()
 require "types".export()
 
-regs = SOC.axiRegs{}:instantiate()
-
 local ConvWidth = 4
 local ConvRadius = ConvWidth/2
 
 inSize = { 1920, 1080 }
 padSize = { 1920+16, 1080+3 }
 
+regs = SOC.axiRegs({},SDF{1,padSize[1]*padSize[2]}):instantiate()
+
 local conv = Module{ ar(u(8),ConvWidth,ConvWidth),
 function(inp)
   inp = Map{AddMSBs{24}}(inp)

examples/soc_convgenTaps.lua

@@ -6,24 +6,25 @@ local RS = require "rigelSimple"
 local C = require "examplescommon"
 require "generators".export()
 require "types".export()
+local SDF = require "sdf"
 
 local ConvWidth = 4
 local ConvRadius = ConvWidth/2
 
-regs = SOC.axiRegs{
+inSize = { 1920, 1080 }
+padSize = { 1920+16, 1080+3 }
+
+regs = SOC.axiRegs({
   coeffs={ar(u(32),ConvWidth,ConvWidth),
           {4, 14, 14,  4,
            14, 32, 32, 14,
            14, 32, 32, 14,
-           4, 14, 14,  4}}}:instantiate()
-
-inSize = { 1920, 1080 }
-padSize = { 1920+16, 1080+3 }
+           4, 14, 14,  4}}},SDF{1,padSize[1]*padSize[2]}):instantiate()
 
 local conv = Module{ ar(u(8),ConvWidth,ConvWidth),
 function(inp)
   inp = Map{AddMSBs{24}}(inp)
-  local z = Zip(inp,regs.fn.coeffs)
+  local z = Zip(inp,regs.module.coeffs)
   local out = Map{Mul}(z)
   local res = Reduce{Add}(out)
   return RemoveMSBs{24}(Rshift{8}(res))

examples/soc_convtest.lua

@@ -5,8 +5,9 @@ local harness = require "harnessSOC"
 local G = require "generators"
 local RS = require "rigelSimple"
 require "types".export()
+local SDF = require "sdf"
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,8192}):instantiate()
 
 ConvTop = G.Module{
   function(i)

examples/soc_filterseq.lua

@@ -6,9 +6,9 @@ local G = require "generators"
 local RS = require "rigelSimple"
 local types = require "types"
 types.export()
+local SDF = require "sdf"
 
---local Regs = SOC.axiRegs{count={u8,0,"out"}}
-local Regs = SOC.axiRegs{}
+local Regs = SOC.axiRegs({},SDF{1,128*64})
 regs = Regs:instantiate()
 
 OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,

examples/soc_filterseq8.lua

@@ -10,11 +10,9 @@ local types = require "types"
 local J = require "common"
 types.export()
 
---local Regs = SOC.axiRegs{count={u8,0,"out"}}
-local Regs = SOC.axiRegs{}
+local Regs = SOC.axiRegs({},SDF{1,1024})
 regs = Regs:instantiate()
 
---BoolGT = G.Module{"BoolGT",function(i) return G.Not(G.And(G.Not(i[0][1]),i[1][1])) end}
 IdxGT = G.Module{"IdxGT",function(i) return G.GT(i[0][1],i[1][1]) end}
 
 -- input type: {{A,bool},u8} -> {A,u8}

examples/soc_flip.lua

@@ -7,7 +7,7 @@ local C = require "examplescommon"
 local SDF = require "sdf"
 require "types".export()
 
-regs = SOC.axiRegs{}:instantiate(SDF{1,1024})
+regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
 
 local W,H = 128,64
 

examples/soc_flipWrite.lua

@@ -7,7 +7,7 @@ local C = require "examplescommon"
 local SDF = require "sdf"
 require "types".export()
 
-regs = SOC.axiRegs{}:instantiate(SDF{1,1024})
+regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
 
 local W,H = 128,64
 

examples/soc_parread.lua

@@ -6,9 +6,10 @@ local G = require "generators"
 local RS = require "rigelSimple"
 local types = require "types"
 local RM = require "modules"
+local SDF = require "sdf"
 types.export()
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,(128*64)/16}):instantiate()
 
 -- this will use 2 AXI ports to read in parallel at twice the BW
 

examples/soc_read.lua

@@ -3,8 +3,9 @@ local G = require "generators"
 local SOC = require "soc"
 local harness = require "harnessSOC"
 require "types".export()
+local SDF = require "sdf"
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,30*14*9}):instantiate()
 
 PosToAddr = G.Module{ "PosToAddr", ar(u16,2),
   function(loc)

examples/soc_redu8192.lua

@@ -5,10 +5,9 @@ local SOC = require "soc"
 local SDF = require "sdf"
 local types = require "types"
 
-local regs = SOC.axiRegs{}:instantiate()
-
 local cycles = tonumber(string.match(arg[0],"%d+"))
---print("CYCLES",arg[0],cycles)
+
+local regs = SOC.axiRegs({},SDF{1,cycles}):instantiate()
 
 local Conv = G.Module{ "ConvTop", SDF{1,cycles},
   function(i)

examples/soc_regin.lua

@@ -7,8 +7,8 @@ local RS = require "rigelSimple"
 local SDF = require "sdf"
 require "types".export()
 
-local Regs = SOC.axiRegs{offset={u(32),200}}
-regs = Regs:instantiate(SDF{1,1024})
+local Regs = SOC.axiRegs({offset={u(32),200}},SDF{1,1024})
+regs = Regs:instantiate()
 
 print("REGS",Regs.offset)
 

examples/soc_regout.lua

@@ -8,8 +8,8 @@ local types = require "types"
 local SDF = require "sdf"
 types.export()
 
-local Regs = SOC.axiRegs{offset={u(8),200},lastPx={u(8),0,"input"}}
-regs = Regs:instantiate(SDF{1,8192})
+local Regs = SOC.axiRegs({offset={u(8),200},lastPx={u(8),0,"input"}},SDF{1,8192})
+regs = Regs:instantiate()
 
 local AddReg = G.Module{"AddReg",function(i) return G.Add(i,Regs.offset) end}
 

examples/soc_simple.lua

@@ -6,8 +6,9 @@ local G = require "generators"
 local RS = require "rigelSimple"
 local types = require "types"
 types.export()
+local SDF = require "sdf"
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
 
 OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
   function(i)
@@ -16,7 +17,4 @@ OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
     return G.AXIWriteBurst{"out/soc_simple"}(offset)
   end}
 
---print(OffsetModule)
---print(OffsetModule:toVerilog())
-
 harness{regs.start, OffsetModule, regs.done}

examples/soc_simple_uniform.lua

@@ -5,9 +5,10 @@ local harness = require "harnessSOC"
 local G = require "generators"
 local RS = require "rigelSimple"
 local types = require "types"
+local SDF = require "sdf"
 types.export()
 
-Regs = SOC.axiRegs{readAddress={u(32),0x30008000},writeAddress={u(32),0x30008000+(128*64)}}
+Regs = SOC.axiRegs({readAddress={u(32),0x30008000},writeAddress={u(32),0x30008000+(128*64)}},SDF{1,128*64})
 regs = Regs:instantiate()
 
 OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,

examples/soc_sort.lua

@@ -8,7 +8,7 @@ local types = require "types"
 local SDF = require "sdf"
 types.export()
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
 
 OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
   function(i)

examples/soc_tokencounter.lua

@@ -8,8 +8,8 @@ local types = require "types"
 local SDF = require "sdf"
 types.export()
 
-local Regs = SOC.axiRegs{startCnt={u32,0,"input"},endCnt={u32,0,"input"}}
-regs = Regs:instantiate(SDF{1,8192})
+local Regs = SOC.axiRegs({startCnt={u32,0,"input"},endCnt={u32,0,"input"}},SDF{1,8192})
+regs = Regs:instantiate()
 
 local RegInOut = G.Module{
   function(i)

examples/soc_unaligned.lua

@@ -5,9 +5,10 @@ local harness = require "harnessSOC"
 local G = require "generators"
 local RS = require "rigelSimple"
 local types = require "types"
+local SDF = require "sdf"
 types.export()
 
-regs = SOC.axiRegs{}:instantiate()
+regs = SOC.axiRegs({},SDF{1,128}):instantiate()
 
 OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
   function(i)
@@ -16,12 +17,8 @@ OffsetModule = G.Module{ "OffsetModule", R.HandshakeTrigger,
     addrStream = G.HS{G.Index{0}}(addrStream)
     addrStream = G.HS{G.AddMSBs{16}}(addrStream)
     addrStream = G.HS{G.Add{3}}(addrStream)
-    --addrStream = G.HS{G.Print}(addrStream)
     local readStream = G.AXIRead{"frame_128.raw",128*64}(addrStream)
     return G.AXIWriteBurstSeq{"out/soc_unaligned",{128,1},0}(readStream)
   end}
 
---print(OffsetModule)
---print(OffsetModule:toVerilog())
-
 harness{regs.start, OffsetModule, regs.done}

examples/soc_underflow.lua

@@ -10,22 +10,7 @@ types.export()
 
 
 -- test underflow block
-
-regs = SOC.axiRegs{}:instantiate()
-
---[=[
-Top = G.Module{types.null(),function(i)
-                 local o = regs.start(i)
-                 o= G.AXIReadBurstSeq{"frame_128.raw",{128,64},u(8),0}(o)
-                 o= G.HS{G.CropSeq{{128,64},{0,0,0,63},0}}(o)
-                 o=RM.underflow(u8,128*2,128+8,false,nil,true,0)(o)
-                 print("OT",o.type)
-                 o=G.AXIWriteBurstSeq{"out/soc_underflow",{128,2},0}(o)
-                 return regs.done(o)
-               end}
-
-print(Top)
-]=]
+regs = SOC.axiRegs({},SDF{1,128*64}):instantiate()
 
 harness{
   regs.start,

examples/tmux_wide_handshake.lua

@@ -4,6 +4,7 @@ local types = require("types")
 local S = require("systolic")
 local harness = require "harness"
 local C = require "examplescommon"
+local SDF = require "sdf"
 W = 128
 H = 64
 T = 8
@@ -13,7 +14,7 @@ T = 8
 ------------
 ITYPE = types.array2d( types.uint(8), T )
 ------------
-local fifos = { R.instantiateRegistered("f1", RM.fifo(ITYPE,128), {{1,2}}) }
+local fifos = { R.instantiate("f1", RM.fifo( ITYPE, 128, nil, nil, nil, nil, nil, nil, SDF{1,2}) ) } --, {{1,2}}) }
 
 A = R.input( R.Handshake(ITYPE), {{1,2}} )
 

modules/examplescommon.lua

@@ -1025,7 +1025,7 @@ C.fifo = memoize(function(ty,size,nostall,csimOnly,VRLoad,X)
   err( ty~=types.null(), "C.fifo: NYI - FIFO of 0 bit type" )
 
   local inp = R.input(R.Handshake(ty))
-  local regs = {R.instantiateRegistered("f1",RM.fifo(ty,size,nostall,nil,nil,nil,csimOnly,VRLoad))}
+  local regs = {R.instantiate("f1",RM.fifo(ty,size,nostall,nil,nil,nil,csimOnly,VRLoad))}
   local st = R.applyMethod("s1",regs[1],"store",inp)
   local ld = R.applyMethod("l1",regs[1],"load")
   return RM.lambda("C_FIFO_"..tostring(ty).."_size"..tostring(size).."_nostall"..tostring(nostall).."_VR"..tostring(VRLoad), inp, R.statements{ld,st}, regs, "C.fifo", {size=size} )